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数据搜索系统，热门电子元器件搜索 |
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RPC564L60L5BOSY 数据表(PDF) 112 Page - STMicroelectronics |
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RPC564L60L5BOSY 数据表(HTML) 112 Page - STMicroelectronics |
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112 / 137 page  Electrical characteristics RPC56EL60L5 112/137 DocID026934 Rev 1 Figure 11. Pad output delay 3.19 Reset sequence This section shows the duration for different reset sequences. It describes the different reset sequences and it specifies the start conditions and the end indication for the reset sequences. 3.19.1 Reset sequence duration Table 30 specifies the minimum and the maximum reset sequence duration for the five different reset sequences described in Section 3.19.2. VDDE/2 VOH VOL Rising Edge Output Delay Falling Edge Output Delay Pad Data Input Pad Output Table 30. RESET sequences No. Symbol Parameter Conditions TReset Unit Min Typ Max(1) 1TDRB CC Destructive Reset Sequence, BIST enabled 28 34 39 ms 2TDR CC Destructive Reset Sequence, BIST disabled — 500 4200 5000 s 3TERLB CC External Reset Sequence Long, BIST enabled 28 32 37 ms 4TFRL CC Functional Reset Sequence Long — 35 150 400 s 5TFRS CC Functional Reset Sequence Short — 1 4 10 s 1. The maximum value is applicable only if the reset sequence duration is not prolonged by an extended assertion of RESET by an external reset generator. |
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