DALC208SC6Y datasheet(4/12 Pages) STMICROELECTRONICS

4 / 12 page

Technical information

DALC208SC6Y

4/12

Doc ID 16362 Rev 1

Technical information

2.1

Surge protection

The DALC208SC6Y is particularly optimized to perform surge protection based on the rail to

rail topology.

The clamping voltage VCL can be calculated as follow:

VCL+ = VREF2 + VF for positive surges

VCL- = VREF1 - VF for negative surges

with

VF = VT + Rd.Ip

(VF forward drop voltage) / (VT forward drop threshold voltage)

We assume that the value of the dynamic resistance of the clamping diode is typically

Rd = 0.7  and VT = 1.2 V.

For an IEC 61000-4-2 surge Level 4 (Contact Discharge: Vg=8 kV, Rg = 330 ), VREF2 = +5 V,

VREF1 = 0 V, and if in first approximation, we assume that: Ip = Vg / Rg  24 A.

So, we find:

–VCL++23 V

–VCL- -18 V

Note:

The calculations do not take into account phenomena due to parasitic inductances.

2.2

Surge protection application example

If we consider that the connections from the pin REF

2 to VCC and from REF1 to GND are

done by two tracks of 10 mm long and 0.5 mm large; we assume that the parasitic

inductances of these tracks are about 6 nH. So when an IEC 61000-4-2 surge occurs, due

to the rise time of this spike (tr = 1 ns), the voltage VCL has an extra value equal to Lw.dI/dt.

The dI/dt is calculated as: dI/dt = Ip/tr  24 A/ns

The overvoltage due to the parasitic inductances is: Lw.dI/dt = 6 x 24

 144V

By taking into account the effect of these parasitic inductances due to unsuitable layout, the

clamping voltage will be:

–V

CL+ = +23 + 144  167 V

–V

CL- = -18 - 144  -162 V

We can reduce as much as possible these phenomena with simple layout optimization.

It’s the reason why some recommendations have to be followed closely. See Section 2.3:

How to ensure good ESD protection.

DALC208SC6Y 数据表(PDF) 4 Page - STMicroelectronics

DALC208SC6Y 数据表(HTML) 4 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12

数据表下载