L6984 datasheet(12/34 Pages) STMICROELECTRONICS

12 / 34 page

Device description

L6984

12/34

DocID025378 Rev 3

3.1

Output voltage adjustment

No external resistor divider is required to regulate fixed 3.3 V output voltage, connecting FB

to the VCC pin and VBIAS to the regulated output voltage (see Figure 1 on page 1). An

external voltage divider otherwise implements the output voltage adjustability.

Figure 4. Internal voltage divider for 3.3 V output voltage

The error amplifier reference voltage is 0.9 V typical.

The output voltage is adjusted accordingly with the following formula (see Figure 5):

Equation 1

Leading network

The small signal contribution of a simple voltage divider is:

Equation 2

A small signal capacitor in parallel to the upper resistor (see C3 in Figure 5) of the voltage

divider implements a leading network (fzero < fpole) that can improve the dynamic regulation

for boundary application conditions (high fSW / high duty cycle conversion) or a not

optimized board layout.

VOUT

0.9

-------







GDIV s



R2 R3

--------------------

L6984 数据表(PDF) 12 Page - STMicroelectronics