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L6984 数据表(PDF) 23 Page - STMicroelectronics |
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L6984 数据表(HTML) 23 Page - STMicroelectronics |
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23 / 34 page ![]() DocID025378 Rev 3 23/34 L6984 Design of the power components 34 4 Design of the power components 4.1 Input capacitor selection The input capacitor voltage rating must be higher than the maximum input operating voltage of the application. During the switching activity a pulsed current flows into the input capacitor and so its RMS current capability must be selected accordingly with the application conditions. Internal losses of the input filter depend on the ESR value, so usually low ESR capacitors (like multilayer ceramic capacitors) have a higher RMS current capability. On the other hand, given the RMS current value, lower ESR input filter has lower losses and so contributes to higher conversion efficiency. The maximum RMS input current flowing through the capacitor can be calculated as: Equation 13 Where IO is the maximum DC output current, D is the duty cycles, is the efficiency. This function has a maximum at D = 0.5 and, considering = 1, it is equal to IO/2. In a specific application the range of possible duty cycles has to be considered in order to find out the maximum RMS input current. The maximum and minimum duty cycles can be calculated as: Equation 14 and Equation 15 Where V HIGH_SIDE and VLOW_SIDE are the voltage drops across the embedded switches. The peak-to-peak voltage across the input filter can be calculated as: Equation 16 In case of negligible ESR (MLCC capacitor) the equation of CIN as a function of the target VPP can be written as follows: Equation 17 IRMS IO D 2D 2 --------------- – D 2 2 ------- + = DMAX VOUT VLOW_SIDE + VINMIN VLOW_SIDE VHIGH_SIDE – + -------------------------------------------------------------------------------------------------- = DMIN VOUT VLOW_SIDE + VINMAX VLOW_SIDE VHIGH_SIDE – + ---------------------------------------------------------------------------------------------------- = VPP IO CIN fSW ----------------------- 1 D ---- – D D ---- 1D – + ESR IO + = CIN IO VPP fSW ------------------------- 1 D ---- – D D ---- 1D – + = |
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