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LED1642GW 数据表(PDF) 25 Page - STMicroelectronics |
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LED1642GW 数据表(HTML) 25 Page - STMicroelectronics |
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25 / 42 page ![]() DocID024395 Rev 6 25/42 LED1642GW Configuration register 42 8.6 SDO delay (CFG-13) Usually in SDO terminal, data are shifted out the rising edge of CLK signal (with a propagation delay of about 15 ns - signal (a) in Figure 21). The device has the possibility to shift data out the falling edge of the CLK signal (with few ns of propagation delay - signal (b) in Figure 21). This feature is active when CFG -13 bit of the configuration register is "1". Default setting for this bit is "0" hence the SDO delay is not activated by default. This feature is particularly useful when some devices are connected in daisy chain configuration with mismatched propagation delays, between CLK and SDO data path (board routing). Figure 17. Output TON (current rise time) CFG - 12 = CFG - 11 = 0 Figure 18. Output TOFF (current fall time) CFG - 2 = CFG - 11 = 0 AM13698V1 AM13699V1 Figure 19. Output TON (current rise time) CFG - 12 = CFG - 11 = 1 Figure 20. Output TOFF (current fall time) CFG - 12 = CFG - 11 = 1 AM13700V1 AM13701V1 |
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