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LED1642GW 数据表(PDF) 27 Page - STMicroelectronics

部件名 LED1642GW
功能描述  16 channel LED driver with error detection current gain control
PDF  42 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

LED1642GW 数据表(HTML) 27 Page - STMicroelectronics

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LED1642GW
Configuration register
42
Figure 22. Gradual output delay
8.8
PWM counter setting and brightness register (CFG-15)
The brightness of each channel can be adjusted through a 12/16-bit PWM grayscale
brightness control according to the PWM counter selection (configuration register CFG -15
bit). Brightness data is loaded by the SDI pin in a 16-bit shift register. Once 16-bit has been
loaded (first input bit of brightness word is MSB, 16th bit is LSB), the digital word is moved to
the corresponding temporary buffer (first word is the brightness of channel 15, the last one
is for channel 0) using the appropriate key shown in Table 7 ("data latch"). One "data latch"
key must follow each 16-bit brightness word except the last one. When the last brightness
word is loaded (channel 0 brightness data), the key indicated as "global latch" in Table 7
must be used. This action moves the word from the shift register to the temporary buffer
through the OUT0 and, at the same time, transfers all data of the 16 temporary buffers (16
x16-bit string) to the corresponding brightness registers (see also Figure 28).
The PWM signals are generated by comparing the content of the brightness registers to a
16-bit or 12-bit counter, according to the CFG-15 bit status. The counter's clock source is
provided to the PWCLK pin. In case of selection of 12-bit PWM counter, the four most
significant bits of each brightness data word are ignored. However, each of sixteen
brightness data words must be 16-bit long.The brightness register default value is "0",
unless this value is changed, the LED brightness is minimum. Figure 27 shows this function
in the schematic.
PWCLK must be a square wave signal, duty cycle is not important but the minimum width
has to be above 20 ns, max. frequency has to be 30 MHz (pay attention the minimum output
ON time). Just after the device startup (brightness counter reset), before applying PWCLK
signal, all channels are in power-on condition if the brightness register values are not
zeroed.
AM13703V1



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