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STL40N10F7 数据表(PDF) 4 Page - STMicroelectronics |
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STL40N10F7 数据表(HTML) 4 Page - STMicroelectronics |
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4 / 15 page ![]() Electrical characteristics STL40N10F7 4/15 DocID024671 Rev 3 2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4: On/Off states Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)DSS Drain-source breakdown voltage ID = 250 μA, VGS = 0 V 100 V IDSS Zero gate voltage drain current VGS = 0 VDS = 100 V 10 µA VGS = 0 , VDS = 100 V, TC = 125° C 100 μA IGSS Gate-body leakage current VDS = 0, VGS= +20 V 100 nA VGS(th) Gate threshold voltage VDS = VGS , ID = 250 μA 3 4.5 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID= 10 A 0.02 0.024 Ω Table 5: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Input capacitance VDS = 50 V, f = 1 MHz, VGS = 0 V - 1270 - pF Coss Output capacitance - 290 - pF Crss Reverse transfer capacitance - 24 - pF Qg Total gate charge VDD = 50 V, ID = 32 A, VGS = 10 V (see Figure 14: "Test circuit for gate charge behavior") - 119 - nC Qgs Gate-source charge - 9 - nC Qgd Gate-drain charge - 4.5 - nC Table 6: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time VDD = 50 V, ID = 16 A, RG = 4.7 Ω, VGS = 10 V (see Figure 13: "Test circuit for resistive load switching times") - 12 - ns tr Rise time - 17.5 - ns td(off) Turn-off delay time - 22 - ns tf Fall time - 5.6 - ns |
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