STM32F401CB datasheet(17/134 Pages) STMICROELECTRONICS

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Functional overview

STM32F401xB STM32F401xC

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DocID024738 Rev 5

3.8

DMA controller (DMA)

The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8

streams each. They are able to manage memory-to-memory, peripheral-to-memory and

memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,

support burst transfer and are designed to provide the maximum peripheral bandwidth

(AHB/APB).

The two DMA controllers support circular buffer management, so that no specific code is

needed when the controller reaches the end of the buffer. The two DMA controllers also

have a double buffering feature, which automates the use and switching of two memory

buffers without requiring any special code.

Each stream is connected to dedicated hardware DMA requests, with support for software

trigger on each stream. Configuration is made by software and transfer sizes between

source and destination are independent.

The DMA can be used with the main peripherals:

•

SPI and I2S

•

I2C

•

USART

•

General-purpose, basic and advanced-control timers TIMx

•

SD/SDIO/MMC host interface

•

ADC

3.9

Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels,

and handle up to 62 maskable interrupt channels plus the 16 interrupt lines of the

Cortex®-M4 with FPU.

•

Closely coupled NVIC gives low-latency interrupt processing

•

Interrupt entry vector table address passed directly to the core

•

Allows early processing of interrupts

•

Processing of late arriving, higher-priority interrupts

•

Support tail chaining

•

Processor state automatically saved

•

Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimum interrupt

latency.

3.10

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 21 edge-detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 81 GPIOs can be connected

to the 16 external interrupt lines.

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