GRSTz

VDD33

VDD

MISC_IO

TUSB8041

www.ti.com

SLLSEE4D – JUNE 2014 – REVISED JANUARY 2016

7.6 Timing Requirements, Power-Up

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

ms

VDD and VDD33 stable before de-assertion of GRSTz

3

ms

0.1

µs

0.1

µs

VDD33 supply ramp requirements

0.2

100

ms

VDD supply ramp requirements

0.2

100

ms

(1)

An active reset is required if the VDD33 supply is stable before the VDD11 supply. This active Reset shall meet the 3ms power-up delay

counting from both power supplies being stable to the de-assertion of GRSTz.

(2)

There is no power-on relationship between VDD33 and VDD unless GRSTz is only connected to a capacitor to GND. Then VDD must

be stable minimum of 10

μs before the VDD33.

(3)

MISC pins sampled at de-assertion of GRSTz: FULLPWRMGMTz, GANGED, PWRCTL_POL, SMBUSz, BATEN[4:1], and AUTOENz.

Figure 2. Power-Up Timing Requirements

7.7 Hub Input Supply Current

VDD33

VDD

PARAMETER

UNIT

3.3 V

1.1 V

LOW POWER MODES

Power On (after Reset)

2.3

28

mA

Upstream Disconnect

2.3

28

mA

Suspend

2.5

33

mA

ACTIVE MODES (US state / DS State)

3.0 host / 1 SS Device and Hub in U1 / U2

49

225

mA

3.0 host / 1 SS Device and Hub in U0

49

366

mA

3.0 host / 2 SS Devices and Hub in U1 / U2

49

305

mA

3.0 host / 2 SS Devices and Hub in U0

49

508

mA

3.0 host / 3 SS Devices and Hub in U1 / U2

49

380

mA

3.0 host / 3 SS Devices and Hub in U0

49

661

mA

3.0 host / 4 SS Devices and Hub in U1 / U2

49

455

mA

3.0 host / 4 SS Devices and Hub in U0

49

778

mA

3.0 host / 1 SS Device in U0 and 1 HS Device

85

395

mA

3.0 host / 2 SS Devices in U0 and 2 HS Devices

99

554

mA

2.0 host / HS Device

45

63

mA

2.0 host / 4 HS Devices

76

86

mA

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