VD5377CBSW datasheet(56/88 Pages) STMICROELECTRONICS

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VD5377

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Doc ID 022952 Rev 2

CDSOUT_SEL

cds_out_sel

1:0

PRW

Selects the output from the

DMIB controller (going to

motion engine and or video

output data).

0 = CDS frame

2 = exposed frame

3 = black frame

FRAMEDUMP_

PIXDATA

framedump_pixdata

7:0

Pixel data in frame dump

mode. Automatically

increments to next pixel after

a read of this register.

FRAMEDUMP_CTRL

framedump_en

PRW

Frame dump mode enable

0 = Disable

1 = Enable

framedump_start

Frame dump started

framedump_ready

Flag set when a frame is

ready to be read by host,

Pixel[0] is ready in register

FRAMEDUMP_PIXDATA.

framedump_done

Flag set when a complete

frame (400 pixels) has been

read.

pci_test_enable

PRW

Muxed PCI data onto pads

(2 bits nibble + FST + Qclk)

0 = Disable

1 = Enable

framedump_mire

PRW

In frame dump mode outputs

a grey scale image

(pixel_counter)

DEVADDR

i2cs_index_auto_

inc_en

PRW

Auto increment function

Table 32. I2C frame dump registers (continued)

Addr

(Hex)

Signal name

Bit

Type

Default

(Hex)

Comment

VD5377CBSW 数据表(PDF) 56 Page - STMicroelectronics

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