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UT54ACS191E 数据表(PDF) 8 Page - Aeroflex Circuit Technology

部件名 UT54ACS191E
功能描述  Synchronous 4-Bit Up-Down Binary Counters
PDF  12 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AEROFLEX [Aeroflex Circuit Technology]
网页  http://www.aeroflex.com
标志 AEROFLEX - Aeroflex Circuit Technology

UT54ACS191E 数据表(HTML) 8 Page - Aeroflex Circuit Technology

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8
36-00-04-001
Ver. 1.0.0
Aeroflex Microelectronics Solutions - HiRel
Notes:
1. Maximum allowable relative shift equals 50mV.
2. For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25°C per MIL-STD-883 method 1019 condition
A up to the maximum TID level procured.
3. Maximum clock frequency fMAX is the max rate at which the device will count up or down at the given voltage. However, the user must wait the appropriate
UP-to-Qn or Down-to-Qn propagation delay time in order to observe the current counter value.
tPHL8
CTEN to RCO
CL = 50pF
4.5V to 5.5V
2
10
ns
3.0V to 3.6V
2
12
fMAX
3
Maximum clock frequency
CL = 50pF
3.0V to 5.5V
70
MHz
tSU1
D/U setup time before CLK
↑
CL = 50pF
4.5V to 5.5V
8
ns
3.0V to 3.6V
10
tSU2
CTEN low setup time before CLK
↑
CL = 50pF
4.5V to 5.5V
10
ns
3.0V to 3.6V
12
tSU3
A, B, C, D setup time before
LOAD
↑
CL = 50pF
4.5V to 5.5V
4
ns
3.0V to 3.6V
5
tSU4
LOAD high setup time before
CLK
↑
CL = 50pF
4.5V to 5.5V
3
ns
3.0V to 3.6V
4
tH1
D/U hold time after CLK
↑
CL = 50pF
3.0V to 5.5V
0
ns
tH2
CTEN low hold time after CLK
↑
CL = 50pF
4.5v to 5.5V
1
ns
3.0V to 3.6V
2
tH3
A, B, C, D hold time after LOAD
↑
CL = 50pF
3.0V to 5.5V
2
ns
tW
Minimum pulse width
CLK high or low
LOAD low
CL = 50pF
3.0V to 5.5V
7
ns



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