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LM5107

SNVS333E – NOVEMBER 2004 – REVISED MARCH 2016

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9 Layout

9.1 Layout Guidelines

The optimum performance of high and low side gate drivers cannot be achieved without taking due

considerations during circuit board layout. Following points are emphasized.

HB and HS pins to support high peak currents being drawn from VDD during turn-on of the external

MOSFET.

2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be

3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances in the

source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized.

4. Grounding Considerations:

–

The first priority in designing grounding connections is to confine the high peak currents from charging

and discharging the MOSFET gate in a minimal physical area. This will decrease the loop inductance and

minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as

possible to the gate driver.

–

The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground

referenced bypass capacitor and low side MOSFET body diode. The bootstrap capacitor is recharged on

The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length

and area on the circuit board is important to ensure reliable operation.