AD9993BBCZ datasheet(19/56 Pages) AD

19 / 56 page

Data Sheet

AD9993

Rev. A | Page 19 of 56

Figure 24. DACs, Band Gap Reference, On-Chip and Off-Chip RFSADJ_x, DAC Gain Setting, and IQ Calibration

Selecting DAC Output Common-Mode Voltage

Two steps are required to select the common-mode output

voltages for the two DACs. For a common-mode voltage less

than 0.5 V, the CML_A and CML_B pins are grounded. For

common-mode voltages that are greater than or equal to 0.5 V,

connect a 0.1 μF capacitor between CML_A or CML_B and

ground. The second step is to program the DAC_VCM_

VREF_BIT bit field. There are three common-mode level

settings to choose from. This common-mode setting applies to

both DACs.

DAC VOLTAGE REFERENCE

The DACs use a single common voltage reference. An on-chip

band gap reference is provided. Optionally, an off-chip voltage

reference can be used. If an off-chip DAC reference is used, set

the DAC_REF_EXT bit in the DAC_CTRL register to 1. After

reset, the on-chip reference is selected.

DAC GAIN SETTING

Figure 24 is a diagram of the AD9993 DACs gain setting

section. It shows the two transmit DACs, the bypassable built-in

1.0 V band gap reference, and the selectable internal and board

level RFSADJ_x resistors. By default, the on-chip band gap

reference is selected. If using a board level. DAC reference

voltage, write 1 to the DAC_REF_EXT bit of the DAC_CTRL

Each DAC has its own RFSADJ_x set resistor. These resistors can be

on or off chip at the discretion of the user. When the on-chip

resistors are in use, their gain accuracy is factory calibrated.

When the off-chip RFSADJ_x resistors are used, an on-chip IQ

calibration scheme can be employed to maintain accuracy

between DAC pairs. By default, the on-chip RFSADJ_x is selected.

If using a board level RFSADJ_x, write 0 to the DAC_RSET_EN bit

of the DAC_CTRL register.

DAC IQ Gain Calibration

When board level RFSADJ_x resistors are used, the gains of the two

DACs can be better matched by running the automatic DAC IQ

gain calibration procedure. This is done by programming the

DAC_CAL_IQ_CTRL register and observing the

DAC_CAL_IQ_STAT register as follows:

Write 0x23 to DAC_CAL_IQ_CTRL (power up the DAC

clock, enable IQ calibration, and start IQ calibration).

Read the DAC_CAL_IQ_DONE bit of the

DAC_CAL_IQ_STAT register until it goes high.

Write 0x4 to DAC_CAL_IQ_CTRL.

DAC DATAPATH FORMAT SELECTION

At reset, the DAC_BINARY bit in the DAC_DP_FMT register is

set to 0, selecting twos complement as the data input format for

both DACs. To select binary offset, set the DAC_BINARY bit to 1.

DAC TEST TONE GENERATOR DDS

The AD9993 includes a tunable direct digital synthesizer for

DAC output tone generation. When the DDS_EN bit of the

DDS_CTRL register is set to 1, the DDS becomes the digital

signal source for the two DACs. The DDS_CTRL register also

has a clock inversion control and amplitude attenuation

controls. At reset, the 32-bit DDS tuning word in the

DDS_TW1_3, DDS_TW1_2, DDS_TW1_1, and DDS_TW1_0

registers is set to 0x19A00000. This value programs the DDS to

produce a 50 MHz tone at both DAC outputs if the master clock

frequency is 1 GHz (DAC sampling rate = 500 MSPS). The

equation for DDS output frequency is

fDDS = (DDS_TW1/232) × fDAC

NOTE:

DEFAULT VALUES FOR

DAC A GAIN AND

DAC B GAIN ARE

SET AT FACTORY TRIM

FOR IFS = 20mA WITH

DAC_RSET_EN = 1

DAC_A

–0.25V

TO +0.25V

CLKA

CLKB

IOUTP

25Ω

IOUTN

DAC_REF_EXT = 0

REG 0x039[0]

CAL IQ

BAND GAP

TRIM

1.0V

±1%

IMEAS A

DAC_B

IOUTP

25Ω

IOUTN

DAC_CAL_IQ_SEL

REG 0x03C[1]

IMEAS B

–0.25V

TO +0.25V

ON CHIP

DAC_RSET_EN = 0

REG 0x039[1]

1.6kΩ

±2%

DAC_RSET_EN = 1

REG 0x039[1]

1.6kΩ

±2%

0.1µF

1.6kΩ

TRIM

±3%

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