AD9993BBCZ datasheet(21/56 Pages) AD

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Data Sheet

AD9993

Rev. A | Page 21 of 56

Figure 26. MxFE Clock Control

SELECTING CLOCKING OPTIONS

Figure 26 is a block diagram of the MxFE clocking system and

its controls. Options of using either an external master clock or

a master clock generated from the on-chip PLL are provided.

CLKGEN_MODE[1:0] in the CLKGEN_CTRL2 register selects

the PLL multiplier or CLKP/CLKN as the master clock source.

ADC DATAPATH AND DAC DATAPATH FIFOS

In the AD9993, data FIFOs are placed between the ADC core

outputs and the LVDS buffers and drivers. Similarly, on the

DAC side, data FIFOs are placed between the LVDS input

buffers and the DAC cores. These FIFOs absorb the phase

difference between DCI and the DAC sampling clock and

between the ADC sampling clock and DCO. DAC sampling

clock and DCI are locked in frequency but have an unknown

phase relationship. The ADC sampling clock and DCO have the

same characteristics.

FIFOs are eight samples deep. During a start-up register

sequence, both the DAC input datapath FIFOs and the ADC

output data path FIFOs have their read and write pointers

initialized (see the Start-Up Register Sequences section). This

occurs after all clocks in the AD9993 are running and settled.

The pointers are set four data samples apart. The ADC datapath

FIFO depth can be read in the RXFIFO_WR_OFFSET bit field

in the align register. The DAC datapath FIFO depth can be read

as the RXFIFO_THERM[7:0] value in the DAC_FIFO_STS1

constant after initialization when all clocks are running

properly.

LVDS INTERFACES

Each DAC has seven DDR LVDS input data lanes. Each DAC

sample input requires the user to input two 7-bit words to the

interface with appropriate zero stuffing. Each ADC has four

DDR LVDS output data lanes. For each ADC output sample,

four 4-bit words are output.

LVDS ADC Data Link

There are two LVDS ADC buses for the two ADCs. Each LVDS

ADC Data bus has four lanes for 14-bit data output in two full

DDR cycles. A strobe lane is shared by the four ADC LVDS

links to identify the MSB of the 14-bit data. Figure 27 shows one

LVDS ADC output data link with four lanes. Lane 0 to Lane 2

output the 12 MSBs of the 14-bit ADC data. Lane 3 carries the

two LSBs of the 14-bit ADC data and an overrange bit.

LVDS DAC Data Link

There are two LVDS DAC data links for the dual DAC. Each

LVDS DAC data link has seven lanes capable of transmitting

14-bit data in one DDR full cycle. Figure 28 shows one LVDS

DAC input data link with seven lanes.

REFCLK = 31.25MHz

62.5MHz

CLKP

CLKN

MASTER

CLOCK INPUT

TO DAC,

ADC, AND

LVDS

÷2

Reg 0x033[5]

CLKGEN_REFCLK_DIV1

DIFF

REG 0x034[1:0]

CLKGEN_MODE

Reg 0x031[7:0]

SYNTH_INT

8kΩ

1.8V

Reg 0x034[1:0]

CLKGEN_MODE

00 = INTERNAL 1GHz CLOCK

11 = EXTERNAL CLOCK (200MHz TO 1GHz)

200MHz TO

1000MHz

Reg 0x031[7:0]

PLL Input Freq | SYNTH_INT

31.25MHz | 0x80

62.5MHz | 0x40

100Ω

15kΩ

PLL

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