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ADC08060 数据表(PDF) 15 Page - National Semiconductor (TI) |
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ADC08060 数据表(HTML) 15 Page - National Semiconductor (TI) |
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15 / 19 page ![]() Applications Information (Continued) V RT should always be at least 1.0V more positive than VRB to minimize noise. V RM (pin 9) is the center of the reference ladder and should be bypassed to a clean, quiet point in the analog ground plane with a 0.1 µF capacitor. DO NOT allow this pin to float. 2.0 THE ANALOG INPUT The analog input of the ADC08060 is a switch followed by an integrator. The input capacitance changes with the clock level, appearing as 3 pF when the clock is low, and 4 pF when the clock is high. Since a dynamic capacitance is more difficult to drive than is a fixed capacitance, choose an amplifier that can drive this type of load. The LMH6702 has been found to be a good amplifier to drive the ADC08060. Figure 4 shows an example of an input circuit using the LMH6702. Any input amplifier should incorporate some gain as operational amplifiers exhibit better phase margin and transient response with gains above 2 or 3 than with unity gain. If an overall gain of less than 3 is required, attenuate the input and operate the amplifier at a higher gain, as shown in Figure 4. 20006233 FIGURE 3. Driving the reference to force desired values requires driving with a low impedance source. www.national.com 15 |
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