Figure 5 gives an example of a suitable layout. All analog

circuitry (input amplifiers, filters, reference components, etc.)

should be placed together away from any digital compo-

nents.

6.0 DYNAMIC PERFORMANCE

The ADC08060 is ac tested and its dynamic performance is

guaranteed. To meet the published specifications, the clock

source driving the CLK input must exhibit less than 10 ps

(rms) of jitter. For best ac performance, isolating the ADC

clock from any digital circuitry should be done with adequate

buffers, as with a clock tree. See Figure 6.

It is good practice to keep the ADC clock line as short as

possible and to keep it well away from any other signals.

Other signals can introduce jitter into the clock signal. The

clock signal can also introduce noise into the analog path.

7.0 COMMON APPLICATION PITFALLS

Driving the inputs (analog or digital) beyond the power

supply rails. For proper operation, all inputs should not go

more than 300 mV below the ground pins or 300 mV above

the supply pins. Exceeding these limits on even a transient

basis may cause faulty or erratic operation. It is not uncom-

mon for high speed digital circuits (e.g., 74F and 74AC

devices) to exhibit undershoot that goes more than a volt

below ground. A 51

Ω resistor in series with the offending

digital input will usually eliminate the problem.

Care should be taken not to overdrive the inputs of the

ADC08060. Such practice may lead to conversion inaccura-

cies and even to device damage.

Attempting to drive a high capacitance digital data bus.

The more capacitance the output drivers must charge for

each conversion, the more instantaneous digital current is

required from DR V

current spikes can couple into the analog section, degrading

dynamic performance. Buffering the digital data outputs (with

a 74F541, for example) may be necessary if the data bus

capacitance exceeds 10 pF. Dynamic performance can also

be improved by adding 47

Ω to 56Ω series resistors at each

digital output, reducing the energy coupled back into the

converter input pins.

Using an inadequate amplifier to drive the analog input.

As explained in Section 2.0, the capacitance seen at the

input alternates between 3 pF and 4 pF with the clock. This

dynamic capacitance is more difficult to drive than is a fixed

capacitance, and should be considered when choosing a

driving device. The LMH6702 has been found to be a good

device for driving the ADC08060.

Driving the V

not source or sink the current required by the ladder.

As mentioned in Section 1.0, care should be taken to see

that any driving devices can source sufficient current into the

V

pins are not driven with devices than can handle the required

current, these reference pins will not be stable, resulting in a

reduction of dynamic performance.

Using a clock source with excessive jitter, using an

excessively long clock signal trace, or having other

signals coupled to the clock signal trace. This will cause

the sampling interval to vary, causing excessive output noise

and a reduction in SNR performance. The use of simple

gates with RC timing is generally inadequate as a clock

source.

20006237

FIGURE 6. Isolating the ADC Clock from Digital

Circuitry

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