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CLC016 数据表(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 CLC016
功能描述  Data Retiming PLL with Automatic Rate Selection
PDF  20 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

CLC016 数据表(HTML) 4 Page - National Semiconductor (TI)

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Electrical Characteristics (Continued)
(V
CC = 0V, VEE = −5V, RBW = 500Ω;CZ = 0.1 µF; CP = 82 pF; Rn = 3504, CARS = 0.1 µF; unless specified).
Parameter
Conditions
Typ
+25˚C
Min/Max
+25˚C
Min/Max
Full Temp.
Range
Units
STATIC PERFORMANCE
CD, UNL, RDO/RD1
(Note 9)
Current Output — LOW, I
OL
V
OL ≤ VEE+0.5V
800
µA
Current Output — HIGH, I
OH
V
OH ≥ VCC−0.5V
−700
µA
TIMING PERFORMANCE
Delay: SCO to SDO, t
d
200
ps
SCO Duty Cycle
(Note 3)
50
44/56
44/56
%
Rise/Fall Time: SCO, SDO, t
r/tf
20%–80%,R
collector =75Ω
(Note 10)
230
ps
SDO Duty Cycle Distortion
35
ps
Minimum Setup Time:
RDO/RD1 to ACQ/WR, t
SU
420
20
ns
Minimum Hold Time:
ACQ/WR to SS1/SS0, t
h
320
20
ns
Minimum Pulse Width:
ACQ/WR, t
w
520
20
ns
ARS Oscillator Period, t
OSC
(Note 3)
10.5
8.5/15.5
ms
CD Pulse Width, t
PW
(Note 11)
1
µs
MUTE Response Time, t
M
5ns
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined
from tested parameters.
Note 3: J-level spec. is 100% tested at +25˚C.
Note 4: Peak-to-peak jitter is defined as 6 times the rms jitter.
Note 5: Tracking and capture range are specified as a percentage of the input data rate fCLK. The minimum and maximum are guaranteed so long as Rn has been
chosen according to the equation in
Resistor Selection for Data Rates.
Note 6: Average data transition density of 1 transition per 2 bit cells.
Note 7: When the value of RBW changes it is necessary to also change the values of CP and CZ. See Loop Filter Design.
Note 8: This information is provided for system troubleshooting purposes only.
Note 9: RD0/RD1 are inputs when AUTO = 0 and outputs when AUTO = 1.
Note 10: Includes typical pc board capacitance.
Note 11: The CD circuit is a retriggerable one-shot which retriggers on every data transition.
Note 12: Human body model, 1.5 k
Ω in series with 100 pF.
Note 13: To maintain specified performance, SCO/SCO and SDO/SDO should not drop below this level.
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