SER goes high when CD is high and either of the following

conditions is true:

•

The FD is active, causing LHP to go high.

•

The harmonic lock detector determines that the VCO is

running at a harmonic of the input data rate, causing

HLOCK to go high.

Timing diagrams related to locking and unlocking of the PLL

and removal of the input data are given in

Figures 8, 9 and

Figure 10. The term t

Filter Design section. Also, t

phase error to decay to less than 90˚. It is given by the fol-

lowing equation:

t

The ARS oscillator period must be greater than the sum of

t

t

The harmonic lock detector senses if the VCO is locked to a

data rate harmonic (integer multiple) by looking for the pres-

ence of bit changes across 3 consecutive periods of CLK as

shown in Case 1 of

Figure 11. This event occurs on average

25% of the time in random data. HLOCK goes low if the oc-

currence rate is less than 12.5%. When a harmonic lock con-

dition occurs there is at leasta2µs delay for HLOCK to go

high. Case 2 illustrates the situation where CLK is at the 2nd

harmonic of the input data rate and each input bit cell is

double-clocked. Bit changes across three consecutive peri-

ods are never detected and HLOCK goes high.

During intervals of sparse data transitions, the harmonic lock

detector may cause SER to go high. An example of this is

the pathological pattern associated with the SMPTE 259M

video industry standard. For an interval of 50 µs, the input

data transitions can be separated by 20-bit cells; and it ap-

pears to the harmonic lock detector as though the VCO is at

a harmonic rate. So long as these intervals do not exceed

the period of the ARS oscillator, the ARS sub-system will not

increment the 2-bit counter.

the value calculated by the above equation of the sparse

data pattern interval. Figure 12 shows a timing diagram re-

lating to sparse data transition intervals.

In auto-rate mode the user can monitor the RD0/1 bus to de-

termine the automatically selected data rate. Refer to

Table 3

for the correspondence between the data bus state and the

selected rate resistor.

DS100087-19

FIGURE 7. Auto-Rate Select

DS100087-20

FIGURE 8. Data Rate Applied or Moves

within PLL Capture

DS100087-21

FIGURE 9. Data Rate Moves beyond the

PLL Tracking Range

DS100087-22

FIGURE 10. Input Data Removed

DS100087-23

FIGURE 11. Harmonic Lock Detector Operation

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