4

Integrated

Circuit

Systems, Inc.

ICS950201

0460G—08/31/04

Byte 0: Control Register

Byte 1: Control Register

Notes:

1. R= Read only RW= Read and Write

2. PWD = Power on Default

3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways. Wither the

system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert PCI_STOP

functionality via I

In Hardware mode it is not allowed to write to the I

PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped PCI_STOP conditions.

The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it is not allowed to mix these

modes.

In Hardware mode the I

PCI_STOP mode.

Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (I

4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high, CPUCLKC

off, and external resistor termination will bring CPUCLKC low.

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