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ICS950201 数据表(PDF) 1 Page - Integrated Circuit Systems |
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ICS950201 数据表(HTML) 1 Page - Integrated Circuit Systems |
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1 / 16 page ![]() Integrated Circuit Systems, Inc. ICS950201 0460G—08/31/04 Block Diagram Pin Configuration 56-Pin SSOP & TSSOP Frequency Table Recommended Application: CK-408 clock for Intel ® 845 chipset with P4 processor. Output Features: • 3 Differential CPU Clock Pairs @ 3.3V • 7 PCI (3.3V) @ 33.3MHz • 3 PCI_F (3.3V) @ 33.3MHz • 1 USB (3.3V) @ 48MHz • 1 DOT (3.3V) @ 48MHz • 1 REF (3.3V) @ 14.318MHz • 5 3V66 (3.3V) @ 66.6MHz • 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz Features: • Supports spread spectrum modulation, down spread 0 to -0.5%. • Efficient power management scheme through PD#, CPU_STOP# and PCI_STOP#. • Uses external 14.318MHz crystal • Stop clocks and functional control available through I 2C interface. Key Specifications: • CPU Output Jitter <150ps • 3V66 Output Jitter <250ps • CPU Output Skew <100ps, programmable over 800 ps with groups CPU0,1 and CPU2. * These inputs have 150K internal pull-up resistor to VDD. Programmable Timing Control Hub™ for P4™ 2 S F1 S F0 S F U P C ) z H M ( 6 6 V 3 ) z H M ( ] 0 : 2 [ f f u B 6 6 ] 2 : 4 [ 6 6 V 3 ) z H M ( F _ I C P I C P ) z H M ( 00 0 6 6 . 6 66 6 . 6 66 6 . 6 63 3 . 3 3 00 1 0 0 . 0 0 16 6 . 6 66 6 . 6 63 3 . 3 3 01 0 0 0 . 0 0 26 6 . 6 66 6 . 6 63 3 . 3 3 01 1 3 3 . 3 3 16 6 . 6 66 6 . 6 63 3 . 3 3 d i M0 0 e t a t s i r Te t a t s i r Te t a t s i r Te t a t s i r T d i M0 1 2 / K L C T4 / K L C T4 / K L C T8 / K L C T d i M1 0 d e v r e s e Rd e v r e s e Rd e v r e s e Rd e v r e s e R d i M1 1 d e v r e s e Rd e v r e s e Rd e v r e s e Rd e v r e s e R |
类似零件编号 - ICS950201 |
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类似说明 - ICS950201 |
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