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ICS950201 数据表(PDF) 7 Page - Integrated Circuit Systems

部件名 ICS950201
功能描述  Programmable Timing Control Hub??for P4?
PDF  16 Pages
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制造商  ICST [Integrated Circuit Systems]
网页  http://www.icst.com
标志 ICST - Integrated Circuit Systems

ICS950201 数据表(HTML) 7 Page - Integrated Circuit Systems

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7
Integrated
Circuit
Systems, Inc.
ICS950201
0460G—08/31/04
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
VIH
2VDD + 0.3
V
Input Low Voltage
VIL
VSS - 0.3
0.8
V
Input High Current
IIH
VIN = VDD
-5
5
µA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
-5
µA
IIL2
VIN = 0 V; Inputs with pull-up resistors
-200
IDD3.3OP
CL = Full load; Select @ 100 MHz
229
240
360
mA
IDD3.3OP
CL =Full load; Select @ 133 MHz
220
236
360
mA
IDD3.3OP
CL = Full load; Select @ 200 MHz
234
245
360
mA
Powerdown Current
IDD3.3PD
IREF=2.32 mA
25
mA
Input Frequency
Fi
VDD = 3.3 V
14.32
MHz
Pin Inductance
Lpin
7
nH
CIN
Logic Inputs
5
pF
COUT
Output pin capacitance
6
pF
CINX
X1 & X2 pins
27
45
pF
Transition time
1
Ttrans
To 1st crossing of target frequency
3
ms
Settling time
1
Ts
From 1st crossing to 1% target frequency
3
ms
Clk Stabilization
1
TSTAB
From VDD = 3.3 V to 1% target frequency
3
ms
tPZH,tPZL Output enable delay (all outputs)
1
10
ns
tPHZ,tPLZ Output disable delay (all outputs)
1
10
ns
1Guaranteed by design, not 100% tested in production.
Delay
1
Input Capacitance
1
Input Low Current
Operating Supply
Current



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