EM78P447SAP datasheet(11/55 Pages) EMC

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EM78P447S

OTP ROM

4. R3 (Status Register)

PS1

PS0

• Bit 7 (GP) General read/write bit.

• Bits 6 (PS1) ~ 5 (PS0) Page select bits. PS1~PS0 are used to pre-select a program memory page.

When executing a "JMP", "CALL", or other instructions which causes the program counter to change

(e.g. MOV R2, A), PS1~PS0 are loaded into the 11th and 12th bits of the program counter and select

one of the available program memory pages. Note that RET (RETL, RETI) instruction does not

change the PS0~PS1 bits. That is, the return will always be to the page from where the subroutine

was called, regardless of the PS1~PS0 bits current setting.

PS1

PS0

Program memory page [Address]

Page 0 [000-3FF]

Page 1 [400-7FF]

Page 2 [800-BFF]

Page 3 [C00-FFF]

• Bit 4 (T) Time-out bit. Set to 1 with the "SLEP" and "WDTC" commands, or during power up, and

reset to 0 with the WDT time-out.

• Bit 3 (P) Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a

"SLEP" command.

• Bit 2 (Z) Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero.

• Bit 1 (DC) Auxiliary carry flag.

• Bit 0 (C) Carry flag

5. R4 (RAM Select Register)

• Bits 7~6 determine which bank is activated among the 4 banks.

• Bits 5~0 are used to select the registers (address: 00~3F) in the indirect addressing mode.

• If no indirect addressing is used, the RSR can be used as an 8-bit general-purpose read/writer

• See the configuration of the data memory in Fig. 4.

6. R5~R7 (Port 5 ~ Port7)

• R5, R6 and R7 are I/O registers

7. R8~R1F and R20~R3E (General Purpose Register)

• R8~R1F, and R20~R3E (including Banks 0~3) are general-purpose registers.

This specification is subject to change without prior notice.

06.25.2003 (V1.1)

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