Application Hints

10 DIGITAL INTERFACE

These DACs are designed to provide all of the necessary

digital input circuitry to permit a direct interface to a wide

variety of microprocessor systems The timing and logic lev-

el convention of the input control signals allow the DACs to

be treated as a typical memory device or IO peripheral with

no external logic required in most systems Essentially

these DACs can be mapped as a two-byte stack in memory

(or IO space) to receive their 12 bits of input data in two

successive 8-bit data writing sequences The DAC1230 se-

ries is intended for use in systems with an 8-bit data bus

The DAC1208 series provides all 12 digital input lines which

can be externally configured to be controlled from an 8-bit

bus or can be driven directly from a 16-bit data bus

All of the digital inputs to these DACs contain a unique

threshold regulator circuit to maintain TTL voltage level

Any input can also be driven from higher voltage CMOS

logic levels in non-microprocessor based systems To pre-

vent damage to the chip from static discharge all unused

shooting aid if any digital input is inadvertently left floating

the DAC will interpret the pin as a logic ‘‘1’’

Double buffered digital inputs allow the DAC to internally

format the 12-bit word used to set the current switching R-

2R ladder network (see section 20) from two 8-bit data

write cycles

Figures 1 and 2 show the internal data regis-

ters and their controlling logic circuitry The timing diagrams

for updating the DAC output are shown in sections 11 12

and 13 for three possible control modes The method used

depends strictly upon the particular application

FIGURE 1 DAC1208 DAC1209 DAC1210 Functional Diagram

TLH5690 – 6

FIGURE 2 DAC1230 DAC1231 DAC1232 Functional Diagram

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