DAC1210 datasheet(13/18 Pages) NSC

13 / 18 page

Application Hints (Continued)

Transient response and settling time of the op amp are im-

portant in fast data throughput applications The largest sta-

bility problem is the feedback pole created by the feedback

resistance RFb and the output capacitance of the DAC

This appears from the op amp output to the (b) input and

includes the stray capacitance at this node Addition of a

lead capacitance CC in Figure 9 greatly reduces overshoot

and ringing at the output for a step change in DAC output

current

211 Zero and Full-Scale Adjustments

For accurate conversions the input offset voltage of the

output amplifier must always be nulled Amplifier offset er-

rors create an overall degradation of DAC linearity

The fundamental purpose of zeroing is to make the voltage

appearing at the DAC outputs as near 0 VDC as possible

This is accomplished by shorting out RFb the amplifier feed-

back resistor and adjusting the vOS nulling potentiometer of

the op amp until the output reads zero volts This is done of

course with an applied digital code of all zeros if IOUT1 is

driving the op amp (all ones for IOUT2) The short around

RFb is then removed and the converter is zero adjusted

A unique feature of this series of DACs is that the full-scale

or gain error is guaranteed to be negative The gain error

specification is a measure of how close the value of the

internal feedback resistor RFb matches the R-2R ladder

resistors A negative gain error indicates that RFb is a small-

er resistance value than it should be To adjust this gain

error some resistance must always be added in series with

RFb The 50X potentiometer shown is sufficient to adjust

the worst-case gain error for these devices

22 Bipolar Output Voltage from a Fixed Reference

The addition of a second op amp to the unipolar circuit can

generate a bipolar output voltage from a fixed reference

voltage This in effect gives sign significance to the MSB of

the digital input word to allow two quadrant multiplication of

the reference voltage The polarity of the reference can also

be reversed to realize full 4-quadrant multiplication This cir-

cuit is shown in

Figure 10

This configuration features several improvements over ex-

isting circuits for a bipolar output shown with other multiply-

ing DACs Only the offset voltage of amplifier 1 affects the

linearity of the DAC The offset voltage error of the second

op amp (although a constant output error) has no effect on

linearity In addition this configuration offers a non-interac-

tive positive and negative full-scale calibration procedure

TLH5690-16

VOUT e VREF

Db2048

2048

for 0 s D s 4095

1 LSB e l

VREF

2048

Input Code

Ideal VOUT

MSBLSB

VREF

111111111111

VREF b1 LSB

lVREFl a1 LSB

110000000000

VREF 2

lVREFl 2

100000000000

011111111111

1 LSB

001111111111

VREF

1 LSB

lVREFl

1 LSB

000000000000

VREF

lVREFl

FIGURE 10 Bipolar Output Voltage Configuration

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