cations where the DAC is used in a continuous feedback

control loop and is driven by a binary updown counter or in

function generation circuits where a ROM is continuously

providing DAC data

Only the DAC1208 DAC1209 DAC1210 devices can have

all 12 inputs flow-through Simply grounding CS WR1 WR2

and XFER and tying Byte 1Byte 2 high allows both internal

registers to follow the applied digital inputs (flow-through)

and directly affect the DAC analog output

17 Address Decoding Tips

It is possible to map the MICRO-DACs into system ROM

space to allow more efficient use of existing address decod-

ing hardware The DAC in effect can share the same ad-

dresses of any number of ROM locations The ROM outputs

will only be enabled by a READ of its address (gated by the

system READ strobe) and the DAC will only accept data

that is written to the same address (gated by the system

WRITE strobe)

The Byte 1Byte 2 control function can easily be generated

by the processor’s least significant address bit (A0) by plac-

ing the DAC at two consecutive address locations and utiliz-

ing double-byte WRITE instructions which automatically in-

crement or decrement the address The CS and XFER sig-

nals can then be decoded from the remaining address bits

Care must be taken in selecting the actual address used

for Byte 1 of the DAC to prevent a carry (as a result of

incrementing the address for Byte 2) from propagating

through the address word and changing any of the bits de-

coded for CS or XFER

Figure 5 shows how to prevent this

effect

The same problem can occur from a borrow when an auto-

decremented address is used but only if the processor’s

address outputs are inverted before being decoded

18 Control Signal Timing

When interfacing these MICRO-DACs to any microproces-

sor there are two important time relationships that must be

considered to insure proper operation The first is the mini-

mum WR strobe pulse width which is specified as 320 ns for

typically a pulse width of only 250 ns is adequate A second

consideration is that the guaranteed minimum data hold

time of 90 ns should be met or erroneous data can be

latched This hold time is defined as the length of time data

must be held valid on the digital inputs

after a qualified (via

CS)WR strobe makes a low to high transition to latch the

applied data

If the controlling device or system does not inherently meet

these timing specs the DAC can be treated as a slow mem-

ory or peripheral and utilize a technique to extend the write

strobe A simple extension of the write time by adding a

wait state can simultaneously hold the write strobe active

and data valid on the bus to satisfy the minimum WR pulse

Write

Address Bits

Cycle

15

2

1

0

First

01

(Byte 1)

Decoded to

Second

Address DAC

1

0

(Byte 2)

Starting with a 0 prevents a carry on address incrementing

Used as Byte 1Byte2 Control

FIGURE 5

TLH5690-12

FIGURE 6 Accommodating a High Speed System

X

Y

9