8705BY

www.icst.com/products/hiperclocks.html

REV. G JUNE 16, 2004

12

Integrated

Circuit

Systems, Inc.

ICS8705

C4

0.1uF

VDD

VDD

R4

1K

Zo = 50

VDD

R7

10 - 15

VDD

R2

43

RD1

Not Install

(U1-24)

(U1-32)

Logic Input Pin Examples

C3

0.1uF

R5

1K

C7

0.1uF

To Logic

Input

pins

(U1-9)

VDD

U1

ICS8705

1

2

3

4

5

6

7

8

17

18

19

20

21

22

23

24

SEL0

SEL1

CLK0

nc

CLK1

nCLK1

CLK_SEL

MR

Q2

GND

Q3

VDDO

Q4

GND

Q5

VDDO

VDD=3.3V or 2.5V

To Logic

Input

pins

R4

43

VDD

C16

10u

R1

43

C2

0.1uF

Zo = 50

Zo = 50

(U1-12)

(U1-16)

(U1-28)

SEL1

RU2

Not Install

VDDA

C1

0.1uF

Ro ~ 7 Ohm

Driv er_LVCMOS

(U1-20)

SEL0

C5

0.1uF

Set Logic

Input to

'1'

RU1

1K

Set Logic

Input to

'0'

C6

0.1uF

RD2

1K

C11

0.01u

The schematic of the ICS8705 layout example is shown in

Figure 4A. The ICS8705 recommended PCB board layout

for this example is shown in

Figure 4B. This layout example is

used as a general guideline. The layout in the actual system will

depend on the selected component types, the density of the

components, the density of the traces, and the stack up of the

P.C. board.