8705BY

www.icst.com/products/hiperclocks.html

REV. G JUNE 16, 2004

13

Integrated

Circuit

Systems, Inc.

ICS8705

Other

signals

GND

VDDA

R7

C7

50 Ohm

Trace

C11

VIA

C16

Pin 1

R2

U1

C5

50 Ohm

Trace

VDD

R1

C2

C4

C6

C1

C3

The following component footprints are used in this layout

example:

All the resistors and capacitors are size 0603.

Place the decoupling capacitors as close as possible to the power

pins. If space allows, placement of the decoupling capacitor on

the component side is preferred. This can reduce unwanted in-

ductance between the decoupling capacitor and the power pin

caused by the via.

Maximize the power and ground pad sizes and number of vias

capacitors. This can reduce the inductance between the power

and ground planes and the component power and ground pins.

The RC filter consisting of R7, C11, and C16 should be placed

as close to the V

Poor signal integrity can degrade the system performance or

cause system failure. In synchronous high-speed digital systems,

the clock signal is less tolerant to poor signal integrity than other

signals. Any ringing on the rising or falling edge or excessive ring

back can cause system failure. The shape of the trace and the

trace delay might be restricted by the available space on the board

and the component location. While routing the traces, the clock

signal traces should be routed first and should be locked prior to

routing other signal traces.

• The differential 50

Ω output traces should have same

length.

• Avoid sharp angles on the clock trace. Sharp angle

turns cause the characteristic impedance to change on

the transmission lines.

• Keep the clock traces on the same layer. Whenever pos-

sible, avoid placing vias on the clock traces. Placement

of vias on the traces can affect the trace characteristic

impedance and hence degrade signal integrity.

• To prevent cross talk, avoid routing other signal traces in

parallel with the clock traces. If running parallel traces is

unavoidable, allow a separation of at least three trace

widths between the differential clock trace and the other

signal trace.

• Make sure no other signal traces are routed between the

clock trace pair.

• The series termination resistors should be located as

close to the driver pins as possible.