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ICS8705 数据表(PDF) 9 Page - Integrated Circuit Systems |
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ICS8705 数据表(HTML) 9 Page - Integrated Circuit Systems |
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9 / 17 page ![]() 8705BY www.icst.com/products/hiperclocks.html REV. G JUNE 16, 2004 9 Integrated Circuit Systems, Inc. ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD PROPAGATION DELAY PHASE JITTER & STATIC PHASE OFFSET Q0:Q7 t PD VDDO 2 ➤ VDD 2 CLK1 nCLK1 CLK0 t PW t PERIOD V DDO 2 V DDO 2 V DDO 2 t PW t PERIOD odc = Q0:Q7 (where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on controlled edges) t(Ø) mean = Static Phase Offset ➤ t(Ø) V OH V OL V OH V OL V DDO 2 nCLK1 FB_IN tjit(Ø) = t(Ø) — t(Ø) mean = Phase Jitter CLK1 |
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