DP83257VF datasheet(3/144 Pages) NSC

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10 FDDI Chip Set Overview

National Semiconductor’s next generation FDDI 2-chip set

consists of two components as shown in

Figure 1-1 The

PLAYERa device integrates the features of the DP83231

CRDTM Clock Recovery Device DP83241 CDDTM Clock

Distribution Device and DP8325155 PLAYERTM Physical

Layer Controller In addition the PLAYERa device contains

enhanced SMT support

National Semiconductor’s FDDI TP-PMD Solutions consist

of two componentsthe DP83222 CYCLONETM Twisted

Pair FDDI Stream Cipher Device and the DP83223A

TWISTERTM Twisted Pair FDDI Transceiver Device

For more information on the other devices of the chip set

consult the appropriate datasheets and application notes

11 FDDI 2-CHIP SET

DP8325656-AP57 PLAYERa

Device Physical Layer Controller

The PLAYERa device implements the Physical Layer

(PHY) protocol as defined by the ANSI FDDI PHY X3T95

standard

Features

Single chip FDDI Physical Layer (PHY) solution

Integrated Digital Clock Recovery Module provides en-

hanced tracking and greater lock acquisition range

Integrated Clock Generation Module provides all neces-

sary clock signals for an FDDI system from an external

125 MHz reference

Alternate PMD Interface (DP83256-AP57) supports

UTP twisted pair FDDI PMDs with no external clock re-

covery or clock generation functions required

No External Filter Components

Connection Management (CMT) Support (LEM TNE

React CF

React Auto Scrubbing)

Full on-chip configuration switch

Low Power CMOS-BIPOLAR design using a single 5V

supply

Full duplex operation with through parity

Separate management interface (Control Bus)

Selectable Parity on PHY-MAC Interface and Control

Bus Interface

Two levels of on-chip loopback

4B5B encoderdecoder

Framing logic

Elasticity Buffer Repeat Filter and Smoother

Line state detectorgenerator

Supports single attach stations

dual attach stations

and concentrators with no external logic

DP8325656-AP for SASDAS single path stations

P83257 for SASDAS singledual path stations

In addition the DP83257 contains the additional PHY

Da-

tarequest and PHY

Dataindicate ports required for con-

centrators and dual attach dual path stations

DP83266 MACSITM Device Media

Access Controller and System

Interface

The DP83266 Media Access Controller and System Inter-

face (MACSI) implements the ANSI X3T95 Standard Media

Access Control (MAC) protocol for operation in an FDDI

token ring and provides a comprehensive System Interface

The MACSI device transmits receives repeats and strips

tokens and frames It produces and consumes optimized

data structures for efficient data transfer Full duplex archi-

tecture with through parity allows diagnostic transmission

and self testing for error isolation in point-to-point connec-

tions

The MACSI device includes the functionality of both the

DP83261 BMAC device and the DP83265 BSI-2 device with

additional enhancements for higher performance and reli-

ability

Features

Over 9 Kbytes of on-chip FIFO

5 DMA Channels (2 Output and 3 Input)

125 MHz to 33 MHz operation

Full duplex operation with through parity

Real-time VOID frame stripping indicator for bridges

On-chip Address bit swapping capability

32-bit wide AddressData path with byte parity

Programmable transfer burst sizes of 4 or 8 32-bit

words

Receive frame filtering services

Frame-per-Page mode controllable on each DMA

channel

Demultiplexed Addresses supported on ABus

New multicast address matching

ANSI X3T95 MAC standard defined ring service op-

tions

Supports all FDDI Ring Scheduling Classes (Synchro-

nous Asynchronous etc)

Supports Individual Group Short Long and External

Addressing

Generates Beacon Claim and Void frames

Extensive ring and station statistics gathering

Extension for MAC level bridging

Enhanced SBus compatibility

Interfaces to DRAMs or directly to system bus

Supports frame HeaderInfo splitting

Programmable Big or Little Endian alignment

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