DP83257VF datasheet(7/144 Pages) NSC

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30 Functional Description

The PLAYERa device is comprised of six blocks Clock

Recovery

Receiver

Transmitter

Configuration Switch

Clock Generation and Station Management Support

31 CLOCK RECOVERY MODULE

The Clock Recovery Module accepts a 125 Mbps NRZI data

stream from the external PMD receiver It then provides the

extracted and synchronized data and clock to the Receiver

block

The Clock Recovery Module performs the following opera-

tions

Locks onto and tracks the incoming NRZI data stream

Extracts the data stream and the synchronized 125 MHz

clock

The Clock Recovery Module is implemented using an ad-

vanced digital architecture that replaces sensitive analog

blocks with digital circuitry This allows the PLAYERa de-

vice to be manufactured to tighter tolerances since it is less

sensitive to processing variations that can adversely affect

analog circuits

The Clock Recovery Module is comprised of 5 main func-

tional blocks

Digital Phase Detector

Digital Phase Error Processor

Digital Loop Filter

Digital Phase to Frequency Converter

Frequency Controlled Oscillator

See

Figure 3-1 Clock Recovery Module Block Diagram

DIGITAL PHASE DETECTOR

The Digital Phase Detector has two main functions phase

error detection and data recovery

Phase error detection is accomplished by a digital circuit

that compares the input data (PMID) to an internal phase-

locked 125 MHz reference clock and generates a pair of

error signals The first signal is a pulse whose width is equal

to the phase error between the input data and a reference

clock and the second signal isa4ns reference pulse

These signals are fed into the Digital Phase Error Processor

block

The data recovery function converts the incoming encoded

data stream (PMID) into synchronized data and clock sig-

nals When the circuit is in lock the rising edge of the recov-

ered clock is exactly centered in the recovered data bit cell

The digital phase detector uses a common path for phase

error detection and data recovery so as to minimize clock

Static Alignment Error (SAE) Phase error averaging is also

included so that phase errors generated by positive and

negative PMID edges equally affect the clock recovery cir-

cuit This greatly improves the immunity to Duty Cycle Dis-

tortion (DCD) in the data recovery circuit

DIGITAL PHASE ERROR PROCESSOR

The Digital Phase Error Processor is responsible for sam-

pling the Phase Detector’s phase error outputs and produc-

ing two digital outputs that indicate to the digital loop filter

how to adjust for a difference between the data phase and

reference phases

The Phase Error Processor is designed to eliminate the ef-

fects of different clock edge densities between data sym-

bols and the various line state symbols on the PLL’s loop

gain

TLF11708 – 3

FIGURE 3-1 Clock Recovery Module Block Diagram

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