www.ti.com

PIN CONFIGURATION (NOT TO SCALE)

1

2

3

4

8

7

6

5

V

DD

DGND

SDI

SCLK

V

OUT

AGND

V

REF

CS

1

2

3

4

5

6

7

14

13

12

11

10

9

8

RFB

V

OUT

AGNDF

AGNDS

V

V

CS

V

DD

INV

DGND

LDAC

SDI

NC

SCLK

DAC8830-EP

DAC8831-EP

SGLS334C – AUGUST 2006 – REVISED APRIL 2007

DAC8830ID, DAC8830IBD,

DAC8831ID, DAC8831IBD,

DAC8830ICD (SO-8)

DAC8831ICD (SO-14)

(TOP VIEW)

(TOP VIEW)

TERMINAL FUNCTIONS

TERMINAL

DESCRIPTION

NO.

NAME

DAC8830

1

Analog output of DAC

2

AGND

Analog ground

3

Voltage reference input

4

CS

Chip select input (active low). Data is not clocked into SDI unless CS is low.

5

SCLK

Serial clock input

6

SDI

Serial data input. Data is latched into input register on the rising edge of SCLK.

7

DGND

Digital ground

8

VDD

Analog power supply, 3 V to 5 V

DAC8831

1

RFB

Feedback resistor. Connect to the output of external operational amplifier in bipolar mode.

2

Analog output of DAC

3

AGNDF

Analog ground (Force)

4

AGNDS

Analog ground (Sense)

5

Voltage reference input (Sense). Connect to external voltage reference.

6

Voltage reference input (Force). Connect to external voltage reference.

7

CS

Chip select input (active low). Data is not clocked into SDI unless CS is low.

8

SCLK

Serial clock input

9

NC

No internal connection

10

SDI

Serial data input. Data is latched into input register on the rising edge of SCLK.

Load DAC control input. Active low. When LDAC is Low, the DAC latch is simultaneously updated with the

11

LDAC

content of the input register.

12

DGND

Digital ground

Junction point of internal scaling resistors. Connect to external operational amplifier’s inverting input in bipolar

13

INV

mode.

14

VDD

Analog power supply, 3 V to 5 V

7

Submit Documentation Feedback