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DP84902MS 数据表(PDF) 7 Page - National Semiconductor (TI) |
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DP84902MS 数据表(HTML) 7 Page - National Semiconductor (TI) |
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7 / 16 page ![]() AC Electrical CharacteristicsWrite Mode are guaranteed over operating conditions (see table) unless otherwise specified Symbol Parameter Conditions Min Typ Max Units Test (Note 1) tSU(NRZIO(01)) NRZIO(01) Setup Time wrt WCLK 8 ns (Note A) (positive edge) (see Figures 5 and 8 ) (Note 3) tH(NRZIO(01)) NRZIO(01) Hold Time wrt WCLK 5 ns (Note A) (positive edge) (see Figures 5 and 8 ) (Note 3) tPD1 Propagation Delay of Encoder Precomp WCLK WCLK (positive edge) to CODEOUT Enabled 5 PERIODS (Note B) (positive edge) (Note 2) (see Figures 5 and 7 ) tPD2 Propagation Delay of Encoder Precomp WCLK WCLK (positive edge) to CODEOUT Disabled 4 PERIODS (Note B) (positive edge) (Note 2) (see Figures 5 and 7 ) tPD3 Propagation Delay of Encoder WG Precomp SYNCCLK (positive edge) to First Valid CODE- Enabled 19 PERIODS (Note B) OUT Output (see Figures 5 and 7 ) tPD4 Propagation Delay of Encoder WG Precomp SYNCCLK (positive edge) to First Valid CODE- Disabled 14 PERIODS (Note B) OUT Output (see Figures 5 and 7 ) tSU(EARLY) EARLY Setup Time wrt CODE- OUT (positive edge) or CODEOUT 6 ns (Note A) (negative edge) (see Figures 5 and 8 ) tH(EARLY) EARLY Hold Time wrt CODEOUT (positive edge) or CODEOUT (negative 6 ns (Note A) edge) (see Figures 5 and 8 ) tSU(LATE) LATE Setup Time wrt CODEOUT (positive edge) or CODEOUT (negative 6 ns (Note A) edge) (see Figures 5 and 8 ) tH(LATE) LATE Hold Time wrt CODEOUT (positive edge) or CODEOUT (nega- 6 ns (Note A) tive edge) (see Figures 5 and 8 ) tPW(WCLK) WCLK Pulse Width (High or Low) 10 ns (Note A) (see Figures 5 and 9 ) Note 1 Typical values are specified at 25 C and 5V supply Note 2 A WCLK period is twice the NRZ rate period since a 2-bit interface is used Note 3 This specification is valid for either internal or external WCLK mode of operation Note A This parameter is guaranteed by outgoing testing Note B This specification is provided for information only 7 |
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