SDA

SCL

S

P

STO

LM48822, LM48822TLEVAL

www.ti.com

SNAS456C – MAY 2008 – REVISED MAY 2013

APPLICATION INFORMATION

I

a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open collector). The LM48822

Data on the SDA line must be stable during the HIGH period of SCL. The LM48822 is a transmit/receive slave-

only device, reliant upon the master to generate the SCL signal. Each transmission sequence is framed by a

START condition and a STOP condition Figure 22. Each data word, device address and data, transmitted over

the bus is 8 bits long as is always followed by an acknowledge pulse (Figure 23). The LM48822 device address

is 1100000.

I

SDA is HIGH, is generated, altering all devices on the bus that a device address is being written to the bus.

The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit. R/W = 0

indicates the master is writing to the slave device, R/W = 1 indicates the master wants to read data from the

slave device. The LM48822 is a WRITE-ONLY device and will not respond the R/W = 1. The data is latched in

on the rising edge of the clock. Each address bit must be stable while SDA is HIGH. After the last address bit is

transmitted, the master device releases SDA, during which time, an acknowledge clock pulse is generated by the

slave device. If the LM48822 receives the correct address, the device pulls the SDA line low, generating and

acknowledge bit (ACK).

Once the master device registers the ACK bit, the 8-bit register data word is sent. Each data bit should be stable

while SCL is HIGH. After the 8-bit register data word is sent, the LM48822 sends another ACK bit. Following the

acknowledgement of the register data word, the master issues a STOP bit, allowing SDA to go high while SDA is

high.

Figure 22. Start and Stop Diagram

Copyright © 2008–2013, Texas Instruments Incorporated

Submit Documentation Feedback

9

Product Folder Links: LM48822 LM48822TLEVAL