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STV7697B

Circuit Description

2

Circuit Description

The STV7697B includes all the necessary logic and power circuits to drive the rows of electrodes of

a plasma display panel (PDP). The state of the displayed line is loaded into the shift register. Data

is shifted at each low to high transition of the (CLK) shift clock. After 64 shifts, the first bit presented

at the serial input (SIN) is available at the serial output (SOUT). This output is used to cascade

Schmitt trigger inputs.

The forward / reverse (F/R) input is used to select the direction of the shift register where data input/

output status is set according to the selected direction. In Reverse mode (F/R = low), data is input

on the SOUT pin and output on the SIN pin.

The maximum frequency of the shift clock is 8 MHz.

The clear signal (CLR) resets the shift register data to 0 when it is pulled to a high level.

Shift register outputs (P1, ... P64) are transferred from the shift register to the latch stage when the

latch input (STB) is at low level.

Figure 2:

Table 5: Shift Register Truth Table

F/R

CLK

SIN

SOUT

Comments

H

Rise

In

Out

Forward Shift

H

L or H

In

Out

Steady

L

Rise

Out

In

Reverse Shift

L

L or H

Out

In

Steady

F/R

64-bit Shift Register

P1

P64

SOUT

SIN (SOUT)

STB

BLK

POL

OUT1

OUT64

STV7697B

CLK

Latch

Q1

Q64

Q2

Q63

S64

S1

CLR