Philips Semiconductors

P89LPC920/921/922

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 06 — 21 November 2003

30 of 45

9397 750 12285

© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

8.22 Watchdog timer

The Watchdog timer causes a system reset when it underflows as a result of a failure

to feed the timer prior to the timer reaching its terminal count. It consists of a

programmable 12-bit prescaler, and an 8-bit down counter. The down counter is

decremented by a tap taken from the prescaler. The clock source for the prescaler is

either the PCLK or the nominal 400 kHz Watchdog oscillator. The Watchdog timer

can only be reset by a power-on reset. When the watchdog feature is disabled, it can

be used as an interval timer and may generate an interrupt. Figure 11 shows the

Watchdog timer in watchdog mode. Feeding the watchdog requires a two-byte

sequence. If PCLK is selected as the watchdog clock and the CPU is powered-down,

the watchdog is disabled. The Watchdog timer has a time-out period that ranges from

afew

µs to a few seconds. Please refer to the P89LPC920/921/922 User’s Manual for

more details.

8.23 Additional features

8.23.1

Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor

completely, as if an external reset or watchdog reset had occurred. Care should be

taken when writing to AUXR1 to avoid accidental software resets.

8.23.2

Dual data pointers

The dual Data Pointers (DPTR) provides two different Data Pointers to specify the

address used with certain instructions. The DPS bit in the AUXR1 register selects

one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic ‘0’ so

that the DPS bit may be toggled (thereby switching Data Pointers) simply by

incrementing the AUXR1 register, without the possibility of inadvertently altering other

bits in the register.

(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a

feed sequence.

Fig 11. Watchdog timer in watchdog mode (WDTE = ‘1’).

PRE2

PRE1

PRE0

–

–

WDRUN

WDTOF

WDCLK

WDCON (A7H)

CONTROL REGISTER

PRESCALER

002aaa423

SHADOW

REGISTER

FOR WDCON

8-BIT DOWN

COUNTER

WDL (C1H)

Watchdog

oscillator

PCLK

÷32

MOV WFEED1, #0A5H

MOV WFEED2, #05AH

RESET

see note (1)