P89LPC922FN datasheet(31/45 Pages) PHILIPS

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Philips Semiconductors

P89LPC920/921/922

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 06 — 21 November 2003

31 of 45

9397 750 12285

8.24 Flash program memory

8.24.1

General description

The P89LPC920/921/922 Flash memory provides in-circuit electrical erasure and

programming. The Flash can be read, erased, or written as bytes. The Sector and

Page Erase functions can erase any Flash sector (1 kB) or page (64 bytes). The Chip

Erase operation will erase the entire program memory. In-System Programming and

standard parallel programming are both available. On-chip erase and write timing

generation contribute to a user-friendly programming interface. The

P89LPC920/921/922 Flash reliably stores memory contents even after 10,000 erase

and program cycles. The cell is designed to optimize the erase and programming

mechanisms. The P89LPC920/921/922 uses VDD as the supply voltage to perform

the Program/Erase algorithms.

8.24.2

Features

• Parallel programming with industry-standard commercial programmers.

• In-Circuit serial Programming (ICP) with industry-standard commercial

programmers.

• IAP-Lite allows individual and multiple bytes of code memory to be used for data

storage and programmed under control of the end application.

• Internal ﬁxed boot ROM, containing low-level In-Application Programming (IAP)

routines that can be called from the end application (in addition to IAP-Lite).

• Default serial loader providing In-System Programming (ISP) via the serial port,

located in upper end of user program memory.

• Boot vector allows user-provided Flash loader code to reside anywhere in the

Flash memory space, providing ﬂexibility to the user.

• Programming and erase over the full operating voltage range.

• Read/Programming/Erase using ISP/IAP/IAP-Lite.

• Any ﬂash program or erase operation in 2 ms.

• Programmable security for the code in the Flash for each sector.

• >100,000 typical erase/program cycles for each byte.

• 10 year minimum data retention.

8.24.3

ISP and IAP capabilities of the P89LPC920/921/922

Flash organization: The P89LPC920/921/922 program memory consists of

two/four/eight 1 kB sectors. Each sector can be further divided into 64-byte pages. In

addition to sector erase, page erase, and byte erase, a 64-byte page register is

included which allows from 1 to 64 bytes of a given page to be programmed at the

same time, substantially reducing overall programming time. An In-Application

Programming (IAP) interface is provided to allow the end user’s application to erase

and reprogram the user code memory. In addition, erasing and reprogramming of

user-programmable bytes including UCFG1, the Boot Status Bit and the Boot Vector

are supported. As shipped from the factory, the upper 512 bytes of user code space

contains a serial In-System Programming (ISP) routine allowing for the device to be

programmed in circuit through the serial port.

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