TLC532AI, TLC532AM, TLC533AI, TLC533AM

LinCMOS

™ 8-BIT ANALOG-TO-DIGITAL PERIPHERALS

WITH 5 ANALOG AND 6 DUAL-PURPOSE INPUTS

SLAS070 – D2819, NOVEMBER 1983 – REVISED SEPTEMBER 1986

POST OFFICE BOX 655303

2

description (continued)

(most-significant byte first). In this manner, a microprocessor can access up to 11 external analog inputs or 6

digital signals and the positive reference voltage that may be used for self-test. The A/D conversion uses the

successive-approximation technique and switched-capacitor circuitry. This method eliminates the possibility of

missing codes, nonmonotonicity, and a need for zero or full-scale adjustment. Any one of 11 analog inputs (or

self-test) can be converted to an 8-bit digital word and stored within 10

µs for the TLC532A or 20 µs for

theTLC533A after instructions from the microprocessor are recognized. The on-chip sample-and-hold circuit

automatically minimizes errors due to noise on the analog inputs. Furthermore, differential high-impedance

reference inputs are available to help isolate the analog circuitry from the logic and supply noises while easing

ratiometric conversion and scaling.

The TLC532AI and TLC533AI are characterized for operation from – 40

°C to 85°C. The TLC532AM and

TLC533AM are available in both the N and FN plastic packages and are characterized for operation from – 55

°C

to 125

°C.

functional description

The TLC532A and TLC533A provide direct interface to a microprocessor-based system. Control of the

TLC532A and TLC533A is handled via the 8-line TTL-compatible 3-state data bus, the three control inputs (R/W,

RS, and CS), and the CLK input. Each device contains three 16-bit internal registers — the control register, the

analog conversion data register, and the digital data register.

A high level at the R/W input and a low level at the CS input set the device to output data on the 8-line data bus

for the processor to read. A low level at the R/W input and a low level at the CS input set the device to receive

instructions into the internal control register on the 8-line data bus from the processor. When the device is in

the read mode and the RS input is low, the processor reads the data contained in the analog conversion data

register. However, when the RS input is high, the processor reads the data contained in the digital-data register.

The control register is a write-only register into which the microprocessor writes command instructions for the

device to start A/D conversion and to select the analog channel to be converted. The analog conversion data

register is a read-only register that contains the current converter status and most recent conversion results.

The digital data register is also a read-only register that holds the digital input logic levels from the six

dual-purpose inputs.

Internally each device contains a byte pointer that selects the appropriate byte during two cycles of the CLK input

in a normal 16-bit microprocessor instruction. The internal pointer automatically points to the most significant

(MS) byte after the first complete clock cycle any time that the CS is at the high level for at least one clock cycle.

The device treats the next signal on the 8-line data bus as the MS byte. A low level at the CS input activates

the inputs and outputs and an internal function decoder. However, no data is transferred until the CLK goes high.

The internal byte pointer first points to the MS byte of the selected register during the first clock cycle. After the

first clock cycle in which the MS byte is accessed, the internal pointer switches to the LS byte and remains there

for as long as CS is low. The MS byte of any register may be accessed by either an 8-bit or a 16-bit

microprocessor instruction; however, the LS byte may only be accessed by a 16-bit microprocessor instruction.

Normally, a 2-byte word is written or read from the controlling processor, but a single byte can be read by the

processor by manipulating the CS input. This can be used to read conversion status from the analog conversion

data register or the digital multipurpose input levels from the digital data register. The format and content of each

2-byte word is shown in Figures 1 through 3.