TLC532AI, TLC532AM

LinCMOS

™ 8-BIT ANALOG-TO-DIGITAL PERIPHERALS

WITH 5 ANALOG AND 6 DUAL-PURPOSE INPUTS

SLAS070 – D2819, NOVEMBER 1983 – REVISED SEPTEMBER 1986

POST OFFICE BOX 655303

8

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VOH

High-level output voltage

IOH = – 1.6 mA

2.4

V

VOL

Low-level output voltage

IOL = 1.6 mA

0.4

V

IIH

High level input current

Any digital or Clock input

VIH =5 5V

10

µA

IIH

High-level input current

Any control input

VIH = 5.5 V

1

µA

IIL

Low level input current

Any digital or Clock input

VIL =0

– 10

µA

IIL

Low-level input current

Any control input

VIL = 0

– 1

µA

IOZ

Off state (high impdance state) output current

VO = VCC

10

µA

IOZ

Off-state (high-impdance state) output current

VO = 0

– 10

µA

II

Analog input current (see Note 3)

VI = 0 to VCC

±500

nA

Leakage current between selected channel

and all other analog channels

VI = 0 to VCC, Clock input at 0 V

±400

nA

Ci

Input capacitance

Digital pins 3 thru 10

4

30

pF

Ci

Input capacitance

Any other input pin

2

15

pF

ICC + IREF+ Supply current plus reference current

VCC = VREF+ = 5.5 V,

Outputs open

1.5

3

mA

ICC

Supply current

VCC = 5.5 V

1.4

2

mA

NOTE 3: Analog input current is an average of the current flowing into a selected analog channel input during one full conversion cycle.

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

Linearity error (see Note 4)

±0.5

LSB

Zero error (see Note 5)

±0.5

LSB

Full-scale error (see Note 5)

±0.5

LSB

Total unadjusted error (see Note 6)

±0.5

LSB

Absolute accuracy error (see Note 7)

±1

LSB

tconv

Conversion time (including channel acquisition time)

30

Clock

Cycles

tacq

Channel acquisition time prior to starting conversion

10

Clock

Cycles

ten

Data output enable time (see Note 8)

CL = 50 pF, RL = 3 kΩ

250

ns

tdis

Data output disable time

CL = 50 pF, RL = 3 kΩ

10

ns

t (bus)

Data output rise time

High-impedance to high level

CL =50 pFRL =3kΩ

150

ns

tr(bus) Data output rise time

Low-to-high level

CL = 50 pF, RL = 3 kΩ

300

ns

tf(bus) Data output fall time

High-impedance to low level

CL =50 pFRL =3kΩ

150

ns

tf(bus) Data output fall time

High-to-low level

CL = 50 pF, RL = 3 kΩ

300

ns

† Typical values are at VCC = 5 V, TA = 25°C.

NOTES: 4. Linearity error is the deviation from the best straight line through the A/D transfer characteristics.

5. Zero error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference between

11111111 and the converted output for full-scale input voltage.

6. Total unadjusted error is the sum of liinearity, zero, and full-scale errors.

7. Absolute accuracy error is the maximum difference between an analog value and the nominal midstep value within any step. This

includes all errors including inherent quantization error, which is the

±0.5 LSB uncertainty caused by the A/D converters’ finite

resolution.

8. If chip-select setup time, tsu(CS), is less than 0.14 µs, the effective data output enable time, ten, may extend such that tsu(CS) + ten is

equal to a maximum of 0.475

µs.