typical operating sequence

1

23

1

23456

289

290

twL(reset)

Don’t Care

tsu(A)

Don’t Care

tsu(CS)

tsu(CS)

tsu(A)

Don’t Care

(see Note A)

(see Note B)

tsu(bus)

HI-Z

State

HI-Z

State

ten

ten

ten

Don’t Care

Don’t Care

CLOCK

R

R/W

CS

RS

DATA

BUS

ten

(see Note C)

(see Note D)

(see Note F)

(see Note E)

= HI-Z States

Start Conversion Cycle If SC Bit Is Logic One (High)

Write Cycle

Read Cycle

Write

Cycle

tsu(A)

tsu(A)

tsu(bus)

tsu(bus)

Don’t Care

ten

ten

ten

ten

tsu(A)

tsu(A)

tsu(A)

tsu(bus)

Don’t Care

Don’t Care

ten

MS

Byte

LS

Byte

LS

Byte

LS

Byte

LS

Byte

MS

Byte

LS

Byte

MS

Byte

LS

Byte

MS

Byte

LS

Byte

(see Note C)

(see Note A)

NOTES: A. This is a 16-bit input instruction from the microprocessor being sent to the control data register.

B. This is the 2-byte (16-bit) content of the digital data register being sent to the microprocessor.

C. This is the LS byte (8-bit) content of the analog conversion data register being sent to the microprocessor.

D. This is the LS byte (8-bit) content of the digital data register being sent to the microprocessor.

E. These are MS byte (8-bit), LS byte (8-bit), and LS byte (8-bit) content of the analog conversion data register or digital data register being sent to the microprocessor.

F. This is the 2-byte (16-bit) content of the analog conversion data register being sent to the microprocessor.