LP5521TMSLASHNOPB datasheet(23/48 Pages) TI1

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LP5521

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SNVS441H – JANUARY 2007 – REVISED MAY 2016

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7.5.2.1 Disabled

Each channel can be configured to disabled mode. LED output current is 0 during this mode. Disabled mode

resets PC of respective channel.

7.5.2.2 LOAD Program

LP5521 can store 16 commands for each channel (R, G, B). Each command consists of 16 bits. Because one

LP5521 supports address auto incrementation. Register address is incremented after each 8 data bits. Whole

program memory can be written in one I2C write sequence.

Program memory is defined in the LP5521 register table, 10H to 2FH for R channel, 30H to 4FH for G channel

and 50H to 6FH for B channel. In order to be able to access program memory at least one channel operation

mode needs to be LOAD Program.

Memory writes are allowed only to the channel in LOAD mode. All channels are in hold while one or several

channels are in LOAD program mode, and PWM values are frozen for the channels which are not in LOAD

mode. Program execution continues when all channels are out of LOAD program mode. LOAD Program mode

resets PC of respective channel.

7.5.2.3 RUN Program

RUN Program mode executes the commands defined in program memory for respective channel (R, G, B).

Execution register bits in ENABLE register define how program is executed. Program start position can be

programmed to Program Counter register (see the following tables). By manually selecting the PC start value,

user can write different lighting sequences to the memory, and select appropriate sequence with the PC register.

If program counter runs to end (15) the next command will be executed from program location 0.

If internal clock is used in the RUN program mode, operation mode needs to be written disabled (00b) before

disabling the chip (with CHIP_EN bit or EN pin) to ensure that the sequence starts from the correct program

counter (PC) value when restarting the sequence.

PC registers are synchronized to 32 kHz clock. Delay between consecutive I2C writes to PC registers (09H, 0AH,

0BH) need to be longer than 153 µs (typ.).

Note that entering LOAD program or Direct Control Mode from RUN PROGRAM mode is not allowed. Engine

execution mode should be set to Hold, and Operation Mode to disabled, when changing operation mode from

RUN mode.

Table 11. R Channel PC Register (09H), G CHANNEL PC Register (0AH), B CHANNEL PC Register (0BH)

NAME

BIT

DESCRIPTION

3:0

Program counter value from 0 to 15d

Table 12. ENABLE Register (00H)

NAME

BIT

DESCRIPTION

R_EXEC

5:4

R channel program execution

00b = Hold: Wait until current command is finished then stop while EXEC mode is hold. PC can be read

or written only in this mode.

01b = Step: Execute instruction defined by current R channel PC value, increment PC and change

R_EXEC to 00b (Hold)

10b = Run: Start at program counter value defined by current R channel PC value

11b = Execute instruction defined by current R channel PC value and change R_EXEC to 00b (Hold)

G_EXEC

3:2

G channel program execution

00b = Hold: Wait until current command is finished then stop while EXEC mode is hold. PC can be read

or written only in this mode.

01b = Step: Execute instruction defined by current G channel PC value, increment PC and change

G_EXEC to 00b (Hold)

10b = Run: Start at program counter value defined by current G channel PC value

11b = Execute instruction defined by current G channel PC value and change G_EXEC to 00b (Hold)

LP5521TM/NOPB 数据表(PDF) 23 Page - Texas Instruments

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