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LP5521TM/NOPB 数据表(PDF) 8 Page - Texas Instruments

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部件名 LP5521TM/NOPB
功能描述  LP5521 Programmable Three-Channel LED Driver
PDF  48 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

LP5521TM/NOPB 数据表(HTML) 8 Page - Texas Instruments

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LP5521
SNVS441H – JANUARY 2007 – REVISED MAY 2016
www.ti.com
Product Folder Links: LP5521
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Logic Interface Characteristics (continued)
(V(EN) = 1.65 V...VDD, and limits apply through ambient temperature range –30°C < TA < +85°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC INPUT SCL, SDA, TRIG, CLK_32K
VIL
Input low level
0.2 × V(EN)
V
VIH
Input high level
0.8 × V(EN)
V
II
Input current
–1
1
µA
ƒCLK_32K
Clock frequency
TJ = 25°C
32
kHz
ƒSCL
Clock frequency
400
kHz
LOGIC OUTPUT SDA, TRIG, INT
IOUT = 3 mA (pullup current),
TJ = 25°C
0.3
VOL
Output low level
IOUT = 3 mA (pull-up current)
0.5
V
IL
Output leakage current
1
µA
LOGIC INPUT ADDR_SEL0, ADDR_SEL1
VIL
Input low level
0.2 × VDD
V
VIH
Input high level
0.8 × VDD
V
II
Input current
–1
1
µA
LOGIC OUTPUT GPO, INT (IN GPO STATE)
IOUT = 3 mA, TJ = 25°C
0.3
VOL
Output low level
IOUT = 3 mA
0.5
V
TJ = 25°C
VDD – 0.3
VOH
Output high level
IOUT = –2 mA
VDD – 0.5
V
IL
Output leakage current
1
µA
(1)
Verified by design.
6.9 I
2C Timing Requirements (SDA, SCL)
Limits are for TJ = 25°C
(1)
MIN
MAX
UNIT
ƒSCL
Clock frequency
400
kHz
1
Hold time (repeated) START condition
0.6
µs
2
Clock low time
1.3
µs
3
Clock high time
600
ns
4
Setup time for a repeated START condition
600
ns
5
Data hold time
50
ns
6
Data set-up time
100
ns
7
Rise time of SDA and SCL
20+0.1Cb
300
ns
8
Fall time of SDA and SCL
15+0.1Cb
300
ns
9
Set-up time for STOP condition
600
ns
10
Bus-free time between a STOP and a START condition
1.3
µs
Cb
Capacitive load for each bus line
10
200
pF
Figure 1. I2C Timing Diagram



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