LP8550TLESLASHNOPB datasheet(30/49 Pages) TI1

30 / 49 page

LP8550

SNVS657E – SEPTEMBER 2010 – REVISED SEPTEMBER 2014

www.ti.com

EEPROM CONTROL REGISTER

EE_PROG

R/W

EEPROM programming.

0 = Normal operation

1 = Start the EEPROM programming sequence. EE_INIT must be written 1 before

EEPROM programming can be started. Programs data currently in the EEPROM

registers to non volatile memory (NVM). Programming sequence takes about 200

ms. Programming voltage is generated inside the chip.

EE_READ

R/W

EEPROM read

0 = Normal operation

1 = Reads the data from NVM to the EEPROM registers. Can be used to restore

default values if EEPROM registers are changed during testing.

Programming sequence (program data permanently from registers to NVM):

1. Turn on the chip by writing BL_CTL bit to 1 and BRT_MODE[1:0] to 10b (05h to address 01h)

2. Write data to EEPROM registers (address A0h…A7h).

3. Write EE_INIT to 1 in address 72h. (04h to address 72h).

4. Write EE_PROG to 1 and EE_INIT to 0 in address 72h. (02h to address 72h).

5. Wait 200 ms.

6. Write EE_PROG to 0 in address 72h. (00h to address 72h).

Read sequence (load data from NVM to registers):

1. Turn on the chip by writing BL_CTL bit to 1 and BRT_MODE[1:0] to 10b (05h to address 01h).

2. Write EE_INIT to 1 in address 72h. (04h to address 72h).

3. Write EE_READ to 1 and EE_INIT to 0 in address 72h. (01h to address 72h).

4. Wait 200 ms.

5. Write EE_READ to 0 in address 72h. (00h to address 72h).

Data written to EEPROM registers is effective immediately even if the EEPROM programming sequence has not

been done. When power is turned off, the device, however, loses the data if it is not programmed to the NVM.

During startup device automatically loads the data from NVM to registers.

NOTE

EEPROM NVM can be programmed or read by customer for bench validation.

Programming for production devices should be done in TI production test, where

appropriate checks are performed to confirm EEPROM validity. Writing to EEPROM

Control register of production devices (for burning or reading EEPROM) is not

recommended. If special EEPROM configuration is required, please contact the TI Sales

Office for availability.

8.6.2 EEPROM Bit Explanations

8.6.2.1 EEPROM Register Map

ADDR

A0H

eeprom addr 0

CURRENT[7:0]

A1H

eeprom addr 1

BOOST_FREQ[1:0]

EN_PWM_&_

TEMP_LIM[1:0]

SLOPE[2:0]

I_CTRL

A2H

eeprom addr 2

ADAPTIVE_SPEED[1:0]

ADV_SLOPE

MODE_25/50%

EN_ADAPT

EN_BOOST

BOOST_IMAX

I_SLOPE[1]

_SEL

A3H

eeprom addr 3

UVLO[1:0]

EN_PSPWM

PWM_FREQ[4:0]

A4H

eeprom addr 4

PWM_RESOLUTION[1:0]

EN_I_RES

LED_FAULT_T

I_SLOPE[0]

DRV_HEADR[2:0]

A5H

eeprom addr 5

EN_VSYNC

DITHER[1:0]

VBOOST[4:0]

A6H

eeprom addr 6

PLL[12:5]

A7H

eeprom addr 7

PLL[4:0]

EN_F_RES

HYSTERESIS[1:0]

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