LP8550TLESLASHNOPB datasheet(40/49 Pages) TI1

40 / 49 page

LP8550

SNVS657E – SEPTEMBER 2010 – REVISED SEPTEMBER 2014

www.ti.com

10 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 2.7 V and 22 V. This input supply

should be well-regulated and able to withstand maximum input current and maintain stable voltage without

voltage drop even at load transition condition (start-up or rapid brightness change). The resistance of the input

supply rail should be low enough that the input current transient does not cause drop high enough in the LP8550

supply voltage that can cause false UVLO fault triggering.

If a separate 5-V power rail is used to power LP8550 VLDO/VIN pins, this voltage must be stable 4.5 V to 5 V.

Excessive noise or ripple in this rail can have adverse effect on device performance, so good grounding and

sufficient bypass capacitors must be used. If the input supply is located more than a few inches from the LP8550

additional bulk capacitance may be required in addition to the ceramic bypass capacitors. Depending on device

EEPROM configuration and usage case the boost converter is configured to operate optimally with certain input

voltage range. Examples are seen in the Detailed Design Procedure section. In uncertain cases, it is

recommended to contact a TI Sales Representative for confirmation of the compatibility of the use case,

EEPROM configuration, and input voltage range.

11 Layout

11.1 Layout Guidelines

Figure 33 is a layout recommendation for the LP8550. The figure is used for demonstrating the principle of good

layout. This layout can be adapted to the actual application layout if/where possible.

It is important that all boost components are close to the chip and the high current traces should be wide enough.

By placing the boost component on one side of the chip it is easy to keep the ground plane intact below the high

current paths. This way other chip pins can be routed more easily without splitting the ground plane. If the chip is

placed in the center of the boost components, the I2C lines, LED lines, etc. cut the ground plane below the high

current paths, and it makes the layout design more difficult.

VIN and VLDO need to be as noise-free as possible. Place the bypass capacitors near the corresponding pins and

ground them to as noise-free ground as possible.

Here are some main points to help the PCB layout work:

1. Current loops need to be minimized:

(a) For low frequency the minimal current loop can be achieved by placing the boost components as close to

the SW and SW_GND pins as possible. Input and output capacitor grounds need to be close to each

other.

(b) Minimal current loops for high frequencies can be achieved by making sure that the ground plane is

intact under the current traces. High frequency return currents try to find route with minimum impedance,

which is the route with minimum loop area, not necessarily the shortest path. Minimum loop area is

formed when return current flows just under the “positive” current route in the ground plane, if the ground

plane is intact under the route. Traces from inner pads of the LP8550 need to be routed from below the

part in the second layer so that traces do not split the ground plane under the boost traces or

components.

2. GND plane needs to be intact under the high current boost traces to provide shortest possible return path

and smallest possible current loops for high frequencies.

3. Current loops when the boost switch is conducting and not conducting needs to be on the same direction in

optimal case.

4. Inductor placement should be so that the current flows in the same direction as in the current loops. Rotating

inductor 180 degrees changes current direction.

5. Use separate “noisy” and “silent” grounds. Noisy ground is used for boost converter return current and silent

ground for more sensitive signals, like VIN and VLDO bypass capacitor grounding.

6. Boost output voltage to LEDs need to be taken out “after” the output capacitors, not straight from the diode

cathode.

7. Small (such as 39 pF) bypass capacitor should be placed close to the FB pin.

8. RISET resistor should be grounded to silent ground, since possible ground ripple will show at the LED current.

9. VIN line should be separated from the high current supply path to the boost converter to prevent high

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