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TDA8024AT 数据表(PDF) 21 Page - NXP Semiconductors |
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TDA8024AT 数据表(HTML) 21 Page - NXP Semiconductors |
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21 / 29 page  2004 July 12 21 Philips Semiconductors Product specification IC card interface TDA8024 tf fall time CL = 30 pF; note 5 −− 16 ns δ duty factor (except for fXTAL) CL = 30 pF; note 5 45 − 55 % SR slew rate slew up or down; CL = 30 pF 0.2 −− V/ns Control inputs (pins CLKDIV1, CLKDIV2, CMDVCC, RSTIN and 5V/3V); note 6 VIL LOW-level input voltage −0.3 − +0.3VDD V VIH HIGH-level input voltage 0.7VDD − VDD + 0.3 V ILIL LOW-level input leakage current 0<VIL <VDD −− 1 µA ILIH HIGH-level input leakage current 0<VIH <VDD −− 1 µA Card presence inputs (pins PRES and PRES); note 7 VIL LOW-level input voltage −0.3 − +0.3VDD V VIH HIGH-level input voltage 0.7VDD − VDD + 0.3 V ILIL LOW-level input leakage current 0<VIL <VDD −− 5 µA ILIH HIGH-level input leakage current 0<VIH <VDD −− 5 µA Interrupt output (pin OFF; NMOS drain with integrated 20 k Ω pull-up resistor to VDD) VOL LOW-level output voltage IOL = 2 mA 0 − 0.3 V VOH HIGH-level output voltage IOH = −15 µA 0.75VDD −− V Rpu integrated pull-up resistor 20 k Ω pull-up resistor to VDD 16 20 24 k Ω Protection and limitation ICC(sd) shutdown and limitation current pin VCC − 130 150 mA II/O(lim) limitation current pins I/O, AUX1 and AUX2 −15 − +15 mA ICLK(lim) limitation current pin CLK −70 − +70 mA IRST(lim) limitation current pin RST −20 − +20 mA Tsd shut-down temperature − 150 −°C Timing tact activation time see Fig.7 50 − 220 µs tde deactivation time see Fig.8 50 80 100 µs t3 start of the window for sending CLK to the card see Fig.7 50 − 130 µs t5 end of the window for sending CLK to the card see Fig.7 140 − 220 µs tdebounce debounce time pins PRES and PRES see Fig.10 5 8 11 ms SYMBOL PARAMETER CONDITIONS MIN. TYP MAX. UNIT |
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