LM93 datasheet(41/92 Pages) NSC

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16.0 Registers (Continued)

16.4 BMC ERROR STATUS REGISTERS 40h–47h

The B_Error Status Registers contain several bits that each represent a particular error event that the LM93 can monitor. The

LM93 sets a given bit whenever the corresponding error event occurs. The BMC_ERR bit in the LM93 Status/Control register is

also set if any bit in the BMC Error Status registers is set. If enabled, ALERT is also asserted anytime BMC_ERR is set. The

exception to this is the fixed threshold error status bits in the PROCHOT Error Status registers. They have no influence on

BMC_ERR or ALERT.

Once a bit is set in the BMC Error Status registers, it is not automatically cleared by the LM93 if the error event goes away. Each

bit must be cleared by software. If software attempts to clear a bit while the error condition still exists, and the error is unmasked,

the bit does not clear. If the error is masked, the bit can be cleared even if the error condition still exists.

If the LM93 is in ASF mode, the BMC Error Status registers are both read-to-clear and write-one-to-clear. When not in ASF mode,

the registers are only write-one-to-clear.

Each register described in this section has a column labeled Sleep Masking. This column describes which error events are

masked in various sleep states. The sleep state of the system is communicated to the LM93 by writing to the Sleep State Control

register. If a sleep state in this column has a ‘*’ next to it, it denotes that the error event is optionally masked in that sleep mode,

depending on the Sleep State Mask registers.

16.4.1 Register 40h

B_Error Status 1

Address

Read/

Write

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

Value

40h

RWC

B_Error

Status 1

RES

VRD2

_ERR

VRD1

_ERR

ZN4_

ERR

ZN3_

ERR

ZN2_

ERR

ZN1_

ERR

00h

Bit

Name

R/W

Description

Sleep

Masking

ZN1_ERR

RWC This bit is set when the zone 1 temperature has fallen outside the zone 1

temperature limits.

S3*, S4/5*

ZN2_ERR

RWC This bit is set when the zone 2 temperature has fallen outside the zone 2

temperature limits.

S3*, S4/5*

ZN3_ERR

RWC This bit is set when the zone 3 temperature has fallen outside the zone 3

temperature limits.

none

ZN4_ERR

RWC This bit is set when the zone 4 temperature has fallen outside the zone 4

temperature limits.

none

VRD1_ERR

RWC This bit is set when the VRD1_HOT input has been asserted.

S3, S4/5

VRD2_ERR

RWC This bit is set when the VRD2_HOT# input has been asserted.

S3, S4/5

7:6

RES

Reserved

N/A

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