ESR

OUT

ESR

V

I

R

=

g

21

TPS61253, TPS61254, TPS61256, TPS61258, TPS61259, TPS612592

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SLVSAG8G – SEPTEMBER 2011 – REVISED JUNE 2016

Product Folder Links: TPS61253 TPS61254 TPS61256 TPS61258 TPS61259 TPS612592

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Copyright © 2011–2016, Texas Instruments Incorporated

With a chosen ripple voltage of 20mV, a minimum effective capacitance of 9

μF is needed. The total ripple is

larger due to the ESR of the output capacitor. This additional component of the ripple can be calculated using

Equation 7

(7)

An MLCC capacitor with twice the value of the calculated minimum should be used due to DC bias effects. This

is required to maintain control loop stability. The output capacitor requires either an X7R or X5R dielectric. Y5V

and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive

at high frequencies. There are no additional requirements regarding minimum ESR. Larger capacitors cause

lower output voltage ripple as well as lower output voltage drop during load transients but the total output

capacitance value should not exceed ca. 50µF.

DC bias effect: high cap. ceramic capacitors exhibit DC bias effects, which have a strong influence on the

device's effective capacitance. Therefore the right capacitor value has to be chosen very carefully. Package size

and voltage rating in combination with material are responsible for differences between the rated capacitor value

and it's effective capacitance. For instance, a 10-µF X5R 6.3-V 0603 MLCC capacitor would typically show an

effective capacitance of less than 4 µF (under 5 V bias condition, high temperature).

In applications featuring high pulsed load currents (e.g. TPS61253 based solution) it is recommended to run the

converter with a reasonable amount of effective output capacitance, for instance x2 10-µF X5R 6.3-V 0603

MLCC capacitors connected in parallel.

10.2.2.3 Input Capacitor

Multilayer ceramic capacitors are an excellent choice for input decoupling of the step-up converter as they have

extremely low ESR and are available in small footprints. Input capacitors should be located as close as possible

to the device. While a 4.7-

μF input capacitor is sufficient for most applications, larger values may be used to

reduce input current ripple without limitations.

Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the

power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce

ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even

damage the part. Additional "bulk" capacitance (electrolytic or tantalum) should in this circumstance be placed

10.2.2.4 Checking Loop Stability

The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:

•

Switching node, SW

•

•

These are the basic signals that need to be measured when evaluating a switching converter. When the

switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the

regulation loop may be unstable. This is often a result of board layout and/or L-C combination.

As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between

the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply

when the device operates in PWM mode.

converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin. Because the

temperature dependant, the loop stability analysis has to be done over the input voltage range, load current

range, and temperature range.