PC87591S-VPC datasheet(64/437 Pages) NSC

64 / 437 page

3.0 Power, Reset and Clocks (Continued)

www.national.com

Revision 1.07

Both AVCC and VCC should be applied for correct operation; and although the PC87591x is protected against damage if op-

erated with only one of them (AVCC or VCC), the ADC and DAC modules do not function correctly in such a case and may

cause current leakage. Therefore, ADC and DAC modules should be left at their reset condition (disabled) or disabled by

firmware until AVCC is within the limits specified above. In addition, the AVCC is internally isolated from VCC to enable AVCC

to be externally filtered or driven by a low-noise power supply.

The PC87591x is designed to operate with a Lithium backup battery that supplies voltage up to 3.6V. The PC87591x includes

an internal current-limiting resistor on the VBAT input as required to meet UL regulations.

VDD,VCC and VBAT use a common ground return, named digital ground and marked GND. The analog circuits supplied by

AVCC use a separate ground return, named analog ground and marked AGND. This ensures effective isolation of the analog

modules from noise caused by the digital modules.

The following directives are recommended for the PC87591x power and ground connections (see Figure 11 for the power

supply connections):

Ground Connection

Use two ground planes, one for the digital signals (GND) and one for the analog signals (AGND). The following ground con-

nections should also be made:

●

The analog ground plane (AGND) should be connected at only one point to the digital ground plane (GND). This point

should be located physically near the PC87591x.

●

The analog ground return pin of the PC87591x (AGND) should be connected to the analog ground plane.

●

The decoupling capacitors of the analog supply (AVCC) pin should be connected to the analog ground plane as close

as possible to the AGND pin.

●

The ground reference of the voltage input signals to the ADC module (VIN0-9 in Figure 11) should be connected to

the AGND plane close to the PC87591x.

●

The ground reference of the voltage output signals from the DAC module (VOUT0-3 in Figure 11) should be connected

to the AGND plane close to the PC87591x.

●

All GND pins of the PC87591x must be connected to the GND plane.

●

The decoupling capacitors of the Suspend digital supply (VCC) pin should be located near each VCC-GND pin pair;

one side of each capacitor should be connected to the ground plane.

●

The ground reference of the voltage input signals to the ACM module (KBVIN0-7 in Figure 11) should be connected

to the GND plane close to the PC87591x.

●

The decoupling capacitors of the Host digital supply (VDD) pin should be located near the VDD-GND pair; one side of

each capacitor should be connected to the ground plane.

●

The ground return and the decoupling capacitor of the backup battery supply (VBAT) pin should be located near the

PC87591x; one of the capacitor’s sides should be connected to the ground plane.

Note that low-impedance ground layers improve noise isolation and reduce ground bounce problems.

Power Connection

All PC87591x supply pins must be connected to the appropriate power plane, and decoupling capacitors must be used as

recommended below.

The analog supply pin, AVCC, should be connected to a low-noise power supply that has the same voltage as the digital

supply (3.3V). If the AVCC pin is connected to the same power supply as the VCC pin, it is recommended to use an external

LC or RC filter for the AVCC pin. An example of an LC filter [L1 and (C1+C2)] is shown in Figure 11. An RC filter is obtained

by replacing L1 (in Figure 11) with a 10Ω resistor (not shown in the figure).

Decoupling Capacitors

The following decoupling capacitors should be used to reduce power supply deeps, ground bounce and EMI (refer to

Figure 11 for the position of capacitors, e.g., C1, C2, etc.):

●

Suspend digital supply (VCC): Place one 0.1 µF capacitor (C3) on each VCC-GND pin pair as close as possible to the

pin pair. Also, place one 10

−47 µFC

4 tantalum capacitor on the common net as close as possible to the chip.

●

Host digital supply (VDD): Place one 0.1 µF capacitor (C5) on the VDD-GND pin pair as close as possible to the pin

pair. Also, place one 10-47

µF tantalum capacitor (C6) on the common net as close as possible to the chip.

●

Backup battery (VBAT): Place one 0.1 µF capacitor (C7) on the VBAT pin as close as possible to the pin.

●

Analog supply (AVCC): Place a 0.1 µF capacitor (C2) and a 10-47 µF tantalum capacitor (C1) on the AVCC pin as

close as possible to the pin.

PC87591S-VPC 数据表(PDF) 64 Page - National Semiconductor (TI)

PC87591S-VPC 数据表(HTML) 64 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载