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PC87591S-VPC 数据表(PDF) 99 Page - National Semiconductor (TI) |
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PC87591S-VPC 数据表(HTML) 99 Page - National Semiconductor (TI) |
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99 / 437 page  Embedded Controller Modules (Continued) Revision 1.07 99 www.national.com Pending interrupts, enabled or disabled, can be polled using the Status registers. The CR16B core supports INT0, but the ICU reserves INT0 so that it is not connected to any interrupt source. Maskable Interrupt Vectors Interrupt vector numbers are always positive and are in the range 1016 to 2F16. The IVCT register contains the interrupt vec- tor of the enabled and pending interrupt with the highest priority. The interrupt vector 1016 corresponds to INT0 with the low- est priority; the vector 2F16 corresponds to INT31 with the highest priority. The CR16B core performs an “Interrupt Acknowledge” bus cycle on receiving an enabled maskable interrupt request from the ICU. During the interrupt acknowledge cycle, a byte is read from address 00 FE0016 (IVCT register). The byte read is used as an index in the Dispatch Table to determine the address of the interrupt handler. Although INT0 is not connected to any interrupt source, the IVCT register can return the value 1016. This happens, for ex- ample, when the interrupt request is removed before the interrupt acknowledge cycle. The entry in the Dispatch Table should point to a default interrupt handler that handles this error condition. Pending Interrupts Edge-triggered interrupts are latched by the Interrupt Status register. A pending edge-triggered interrupt is cleared by writing a ‘1’ to the respective bit in the Edge Interrupt Clear register, IECLR0 or IECLR1. A pending level-triggered interrupt is cleared when the interrupt source is not active; note that the interrupt should be cleared at the device/module that drives it by clearing the event status bit. Interrupt mask bits (IENAM register bits) and pending interrupt bits (ISTAT register bits), should be cleared to 0 only when interrupts are disabled; i.e., when bits I and/or E in PSR register (a core register) are 0. Bits in IENAM may be set at any time. Interrupt Priorities The priorities of the maskable interrupts are hard-wired and thus fixed. The interrupts are named INT0 to INT31, where INT0 has the lowest priority and INT31 has the highest priority. Power-Down Modes Interrupt sources that may generate unexpected interrupts in Idle mode should be masked before switching to the power- down mode. External Interrupt Inputs When an MIWU input is disabled, and the respective WKOxx output at the MIWU is connected to the ICU, the MIWU input is fed directly to the ICU. In this case, the interrupt inputs are asynchronous. They are recognized by the PC87591x during cycles in which the input setup and hold time requirements are satisfied. To use an external interrupt which is shared with an I/O port, configure the I/O port to its alternate function (see Section 2.4 on page 54). Interrupt Assignment Table 16 shows the mapping of the ICU maskable interrupts to different functions. For information on mask bits and the clear mechanism for the status bit in internal level interrupts, refer to descriptions of the module that is the interrupt source. Table 16. ICU Interrupt Assignments INT Number Source Type Details Priority INT0 - - Error condition occurred (spurious interrupt) Lowest INT1 External/MIWU Level-High External Interrupt EXWINT20 through the MIWU1 INT2 Internal Level-High Host I/F Keyboard/Mouse channel Output Buffer Empty INT3 Internal Level-High Host I/F Power Management channel 1 or channel 2 Output Buffer Empty INT4 Internal Level-High High-Frequency Clock Generator INT5 Internal Level-High MIWU PSWUINT or WKINTD INT6 External/MIWU Level-High External Interrupt EXWINT23 through the MIWU1 INT7 Internal Level-High MFT16 1 Interrupt (INT1 ORed with INT2) |
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