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PC87591S-VPC 数据表(PDF) 73 Page - National Semiconductor (TI) |
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PC87591S-VPC 数据表(HTML) 73 Page - National Semiconductor (TI) |
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73 / 437 page ![]() 4.0 Embedded Controller Modules (Continued) Revision 1.07 73 www.national.com HOLD field in SZCFGn reg. ≠ 0 WAIT field in SZCFGn reg. ≠ 0 T2 SELn: inactive, WR0-1: inactive; if HOLD field in SZCFGn reg. = 0 data put in TRI-STATE. WAIT field in SZCFGn reg. = 0 Hold cycles completed Address placed on A0-19, WR0-1: activated Data placed on D0-15, SELn: active Internal waits completed HOLD in SZCFGn reg. = 0 Address on A0-19 invalid/changed Data put in TRI-STATE Data placed on D0-15, SELn: active Internal waits corresponding to Wait field in SZCFGn register. T1 T2 Thold Hold cycles according to HOLD field in SZCFGn reg. TIW T3 T1 end begin Note: References to SZCFGn also apply to the IOCFG register. References to SELn also apply to the SELIO signal. Figure 12. Early Write Bus Cycle |
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