VA- = -5V

Parameter

Symbol

Min

Typ

Max

Units

SSC Mode (M/SLP = VD+)

Access Time:

CS Low to SDATA out (DRDY = low)

DRDY falling to MSB (CS = low)

-

-

-

2/fclk

ns

ns

SDATA Delay Time:

SCLK falling to next SDATA bit

-

80

250

ns

SCLK Delay Time

SDATA MSB bit to SCLK rising

-ns

Serial Clock (Out)

Pulse Width High

Pulse Width Low

-

-

-

-

ns

ns

Output Float Delay:

CS high to output Hi-Z (Note 16)

SCLK rising to SDATA Hi-Z

-

-

-

-

ns

ns

SEC Mode (M/SLP = DGND)

Serial Clock (In)

0-

2.5

MHz

Serial Clock (In)

Pulse Width High

Pulse Width Low

200

200

-

-

-

-

ns

ns

Access Time:

CS Low to data valid (Note 17)

-

60

200

ns

Maximum Delay time:

(Note 18)

SCLK falling to new SDATA bit

-

150

310

ns

Output Float Delay:

CS high to output Hi-Z (Note 16)

SCLK falling to SDATA Hi-Z

-

-

60

160

150

300

ns

ns

Notes: 16. If CS is returned high before all data bits are output, the SDATA and SCLK outputs will complete the

current data bit and then go to high impedance.

17. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high

for 2 clock cycles. The propagation delay time may be as great as 2 fclk cycles plus 200 ns. To

guarantee proper clocking of SDATA when using asynchronous CS, SCLK(i) should not be taken high

sooner than 2 fclk + 200 ns after CS goes low.

18. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the

serial port shifting mechanism before falling edges can be recognized.

CS5505/6/7/8

DS59F4

9

CS5505/6/7/8

DS59F5

9